mirror of
https://github.com/yuzu-emu/unicorn.git
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d331b8f7d8
* add x86_64_msr.py test demonstrating setting MSRs and FS/GS segments * x86_64_msr.py: remove references to hooks * x86_64_msr.py: remove references to old global variable
156 lines
4.2 KiB
Python
Executable file
156 lines
4.2 KiB
Python
Executable file
#!/usr/bin/env python
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from unicorn import *
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from unicorn.x86_const import *
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from struct import pack
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import regress
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CODE_ADDR = 0x40000
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CODE_SIZE = 0x1000
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SCRATCH_ADDR = 0x80000
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SCRATCH_SIZE = 0x1000
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SEGMENT_ADDR = 0x5000
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SEGMENT_SIZE = 0x1000
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FSMSR = 0xC0000100
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GSMSR = 0xC0000101
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def set_msr(uc, msr, value, scratch=SCRATCH_ADDR):
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'''
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set the given model-specific register (MSR) to the given value.
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this will clobber some memory at the given scratch address, as it emits some code.
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'''
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# save clobbered registers
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orax = uc.reg_read(UC_X86_REG_RAX)
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ordx = uc.reg_read(UC_X86_REG_RDX)
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orcx = uc.reg_read(UC_X86_REG_RCX)
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orip = uc.reg_read(UC_X86_REG_RIP)
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# x86: wrmsr
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buf = '\x0f\x30'
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uc.mem_write(scratch, buf)
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uc.reg_write(UC_X86_REG_RAX, value & 0xFFFFFFFF)
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uc.reg_write(UC_X86_REG_RDX, (value >> 32) & 0xFFFFFFFF)
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uc.reg_write(UC_X86_REG_RCX, msr & 0xFFFFFFFF)
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uc.emu_start(scratch, scratch+len(buf), count=1)
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# restore clobbered registers
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uc.reg_write(UC_X86_REG_RAX, orax)
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uc.reg_write(UC_X86_REG_RDX, ordx)
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uc.reg_write(UC_X86_REG_RCX, orcx)
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uc.reg_write(UC_X86_REG_RIP, orip)
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def get_msr(uc, msr, scratch=SCRATCH_ADDR):
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'''
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fetch the contents of the given model-specific register (MSR).
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this will clobber some memory at the given scratch address, as it emits some code.
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'''
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# save clobbered registers
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orax = uc.reg_read(UC_X86_REG_RAX)
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ordx = uc.reg_read(UC_X86_REG_RDX)
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orcx = uc.reg_read(UC_X86_REG_RCX)
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orip = uc.reg_read(UC_X86_REG_RIP)
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# x86: rdmsr
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buf = '\x0f\x32'
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uc.mem_write(scratch, buf)
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uc.reg_write(UC_X86_REG_RCX, msr & 0xFFFFFFFF)
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uc.emu_start(scratch, scratch+len(buf), count=1)
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eax = uc.reg_read(UC_X86_REG_EAX)
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edx = uc.reg_read(UC_X86_REG_EDX)
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# restore clobbered registers
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uc.reg_write(UC_X86_REG_RAX, orax)
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uc.reg_write(UC_X86_REG_RDX, ordx)
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uc.reg_write(UC_X86_REG_RCX, orcx)
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uc.reg_write(UC_X86_REG_RIP, orip)
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return (edx << 32) | (eax & 0xFFFFFFFF)
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def set_gs(uc, addr):
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'''
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set the GS.base hidden descriptor-register field to the given address.
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this enables referencing the gs segment on x86-64.
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'''
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return set_msr(uc, GSMSR, addr)
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def get_gs(uc):
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'''
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fetch the GS.base hidden descriptor-register field.
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'''
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return get_msr(uc, GSMSR)
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def set_fs(uc, addr):
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'''
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set the FS.base hidden descriptor-register field to the given address.
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this enables referencing the fs segment on x86-64.
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'''
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return set_msr(uc, FSMSR, addr)
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def get_fs(uc):
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'''
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fetch the FS.base hidden descriptor-register field.
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'''
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return get_msr(uc, FSMSR)
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class TestGetSetMSR(regress.RegressTest):
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def test_msr(self):
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uc = Uc(UC_ARCH_X86, UC_MODE_64)
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uc.mem_map(SCRATCH_ADDR, SCRATCH_SIZE)
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set_msr(uc, FSMSR, 0x1000)
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self.assertEqual(0x1000, get_msr(uc, FSMSR))
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set_msr(uc, GSMSR, 0x2000)
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self.assertEqual(0x2000, get_msr(uc, GSMSR))
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def test_gs(self):
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uc = Uc(UC_ARCH_X86, UC_MODE_64)
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uc.mem_map(SEGMENT_ADDR, SEGMENT_SIZE)
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uc.mem_map(CODE_ADDR, CODE_SIZE)
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uc.mem_map(SCRATCH_ADDR, SCRATCH_SIZE)
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code = '6548330C2518000000'.decode('hex') # x86-64: xor rcx, qword ptr gs:[0x18]
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uc.mem_write(CODE_ADDR, code)
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uc.mem_write(SEGMENT_ADDR+0x18, 'AAAAAAAA')
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set_gs(uc, SEGMENT_ADDR)
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self.assertEqual(SEGMENT_ADDR, get_gs(uc))
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uc.emu_start(CODE_ADDR, CODE_ADDR+len(code))
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self.assertEqual(uc.reg_read(UC_X86_REG_RCX), 0x4141414141414141)
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def test_fs(self):
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uc = Uc(UC_ARCH_X86, UC_MODE_64)
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uc.mem_map(SEGMENT_ADDR, SEGMENT_SIZE)
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uc.mem_map(CODE_ADDR, CODE_SIZE)
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uc.mem_map(SCRATCH_ADDR, SCRATCH_SIZE)
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code = '6448330C2518000000'.decode('hex') # x86-64: xor rcx, qword ptr fs:[0x18]
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uc.mem_write(CODE_ADDR, code)
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uc.mem_write(SEGMENT_ADDR+0x18, 'AAAAAAAA')
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set_fs(uc, SEGMENT_ADDR)
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self.assertEqual(SEGMENT_ADDR, get_fs(uc))
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uc.emu_start(CODE_ADDR, CODE_ADDR+len(code))
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self.assertEqual(uc.reg_read(UC_X86_REG_RCX), 0x4141414141414141)
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if __name__ == '__main__':
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regress.main()
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