Lioncash dcc9420555 Add missing x86_vec regression test ... This was initially supposed to be bundled with the changes in the backported commit: 5bf6d77e4ee258c67c2d7ead94cf266a7b9773e7		2019-02-28 17:08:19 -05:00
..
.gitignore	regress: ignore arm_enable_vfp	2017-02-26 10:50:18 +08:00
00opcode_uc_crash.c
001-bad_condition_code_0xe.c
002-qemu__fatal__unimplemented_control_register_write_0xffb___0x0.c
003-qemu__fatal__wdebug_not_implemented.c
004-segmentation_fault_1.c
005-qemu__fatal__illegal_instruction__0000___00000404.c
006-qemu__fatal__illegal_instruction__0421___00040026.c
arm64_reg_rw_w0_w30.py
arm_bx_unmapped.py
arm_bxeq_hang.py
arm_enable_vfp.c
arm_fp_vfp_disabled.py
arm_init_input_crash.py
arm_movr12_hang.py
arm_vldr_invalid.py
bad_ram.py
block_test.c
callback-pc.py
crash_tb.py
deadlock_1.py
eflags_noset.c	fix merge conflicts	2017-03-10 21:04:33 +08:00
eflags_nosync.c
emu_clear_errors.c
emu_clear_errors.py
emu_stop_in_hook_overrun.c
emu_stop_segfault.py
ensure_typedef_consts_generated.py
fpu_ip.py
fpu_mem_write.py
hang.py
hook_add_crash.py
hook_code_add_del.py
hook_code_stop_emu.py
hook_extrainvoke.c
init.py
invalid_read_in_cpu_tb_exec.c
invalid_read_in_tb_flush_x86_64.c
invalid_write.py
invalid_write_in_cpu_tb_exec_x86_64.c
jmp_ebx_hang.py
jumping.py
leaked_refs.py
LICENSE
Makefile	MSYS test (#852)	2017-06-25 10:11:35 +08:00
map_crash.c
map_write.c
mem_64_c.c
mem_double_unmap.c
mem_exec.c
mem_fuzz.c	tests: fix mem_fuzz.c - FIXME	2017-07-23 16:33:57 +08:00
mem_map_0x100000000.c
mem_map_large.c
mem_nofree.c
mem_protect.c
mem_unmap.c
memleak_arm.c
memleak_arm64.c
memleak_m68k.c
memleak_mips.c
memleak_sparc.c	Fuzz builds ok	2018-10-06 04:55:02 -04:00
memleak_x86.c
memmap.py
memmap_segfault.py
mips_branch_delay.py
mips_branch_likely_issue.c
mips_delay_slot_code_hook.c
mips_except.py
mips_invalid_read_of_size_4_when_tracing.c
mips_kernel_mmu.py
mips_kseg0_1.c
mips_single_step_sp.py
mips_syscall_pc.py
mov_gs_eax.py
movsd.py
nr_mem_test.c
osx_qemu_thread_create_crash.py
potential_memory_leak.py
pshufb.py
reg_write_sign_extension.py
regress.py
regress.sh
rep_hook.py
rep_movsb.c
ro_mem_test.c
run_across_bb.py
rw_hookstack.c
segfault_on_stop.py
sigill.c
sigill2.c
sparc64.py
sparc_jump_to_zero.c
sparc_reg.py
sysenter_hook_x86.c	Makes SYSENTER hookable again on x86	2018-09-03 07:53:48 -04:00
tcg_liveness_analysis_bug_issue-287.py
threaded_emu_start.c	MSYS test (#852)	2017-06-25 10:11:35 +08:00
timeout_segfault.c
translator_buffer.py
vld.py
write_before_map.py
wrong_rip.py
wrong_rip_arm.py
wrong_sp_arm.py
x86_16_segfault.c
x86_64_conditional_jump.py
x86_64_eflags.py
x86_64_msr.py	add 64-bit test demonstrating setting MSRs and FS/GS segments (#901)	2017-09-29 04:26:23 +08:00
x86_eflags.py
x86_fldt_fsqrt.py
x86_gdt.py
x86_self_modifying.elf
x86_self_modifying.py
x86_self_modifying.s
x86_vec.c	Add missing x86_vec regression test	2019-02-28 17:08:19 -05:00