James Hogan ddbea9422c target/mips: Add segmentation control registers ... The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 & CP0_SegCtl2 control the behaviour and required privilege of the legacy virtual memory segments. Add them to the CP0 interface so they can be read and written when CP0_Config3.SC=1, and initialise them to describe the standard legacy layout so they can be used in future patches regardless of whether they are exposed to the guest. Backports commit cec56a733dd2c3fa81dbedbecf03922258747f7d from qemu		2018-03-04 01:00:42 -05:00
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arm	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
i386	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
m68k	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00
mips	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
sparc	tcg: Pass generic CPUState to gen_intermediate_code()	2018-03-03 23:34:18 -05:00