Peter Maydell ddfe550411 arm: Thumb shift operations should not permit interworking branches ... In Thumb mode, the only instructions which can cause an interworking branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike ARM mode, data processing instructions which target the PC do not cause interworking branches. When we added support for doing interworking branches on writes to PC from data processing instructions in commit 21aeb3430ce7ba, we accidentally changed a Thumb instruction to have interworking branch behaviour for writes to PC. (MOV, MOVS register-shifted register, encoding T2; this is the standard encoding for LSL/LSR/ASR/ROR (register).) For this encoding, behaviour with Rd == R15 is specified as UNPREDICTABLE, so allowing an interworking branch is within spec, but it's confusing and differs from our handling of this class of UNPREDICTABLE for other Thumb ALU operations. Make it perform a simple (non-interworking) branch like the others. Backports commit bedb8a6b09c1754c3b9f155750c62dc087706698 from qemu		2018-03-02 14:42:40 -05:00
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arm	arm: Thumb shift operations should not permit interworking branches	2018-03-02 14:42:40 -05:00
i386	i386: Don't override -cpu options on -cpu host/max	2018-03-02 14:22:45 -05:00
m68k	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
mips	target/mips: fix delay slot detection in gen_msa_branch()	2018-03-02 14:15:50 -05:00
sparc	cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap	2018-03-02 10:12:40 -05:00