Hesham Almatary e648455989 RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off ... The current implementation returns 1 (PMP check success) if the address is in range even if the PMP entry is off. This is a bug. For example, if there is a PMP check in S-Mode which is in range, but its PMP entry is off, this will succeed, which it should not. The patch fixes this bug by only checking the PMP permissions if the address is in range and its corresponding PMP entry it not off. Otherwise, it will keep the ret = -1 which will be checked and handled correctly at the end of the function. Backports commit f8162068f18f2f264a0355938784f54089234211 from qemu		2019-08-08 16:55:52 -04:00
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arm	target/arm: Declare some M-profile functions publicly	2019-08-08 15:37:01 -04:00
i386	target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY	2019-06-25 18:59:52 -05:00
m68k	m68k comments break patch submission due to being incorrectly formatted	2019-08-08 14:26:45 -04:00
mips	target/mips: Correct helper for MSA FCLASS.<W|D> instructions	2019-08-08 16:30:15 -04:00
riscv	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	2019-08-08 16:55:52 -04:00
sparc	cpu: Introduce CPUNegativeOffsetState	2019-06-13 15:08:25 -04:00