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unicorn/qemu/target-mips
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Yongbok Kim 46284f1a41
target-mips: implement R6 multi-threading 
MIPS Release 6 provides multi-threading features which replace
pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new
CP0.Config5.VP (Virtual Processor) bit which indicates presence of
multi-threading support which includes CP0.GlobalNumber register and
DVP/EVP instructions.

Backports commit 01bc435b44b8802cc4697faa07d908684afbce4e from qemu
2018-02-20 22:02:40 -05:00
..
cpu-qom.h remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
cpu.c target-mips: implement R6 multi-threading 2018-02-20 22:02:40 -05:00
cpu.h target-mips: implement R6 multi-threading 2018-02-20 22:02:40 -05:00
dsp_helper.c mips: Clean up includes 2018-02-19 00:45:08 -05:00
helper.c mips: Clean up includes 2018-02-19 00:45:08 -05:00
helper.h target-mips: implement R6 multi-threading 2018-02-20 22:02:40 -05:00
lmi_helper.c mips: Clean up includes 2018-02-19 00:45:08 -05:00
Makefile.objs import 2015-08-21 15:04:50 +08:00
mips-defs.h target-mips: fix MIPS64R6-generic configuration 2018-02-17 15:23:21 -05:00
msa_helper.c mips: Clean up includes 2018-02-19 00:45:08 -05:00
op_helper.c target-mips: implement R6 multi-threading 2018-02-20 22:02:40 -05:00
TODO import 2015-08-21 15:04:50 +08:00
translate.c target-mips: implement R6 multi-threading 2018-02-20 22:02:40 -05:00
translate_init.c target-mips: implement R6 multi-threading 2018-02-20 22:02:40 -05:00
unicorn.c Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
unicorn.h armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00