Peter Maydell ed92f3c42b target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check ... The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN bit in short-descriptor translation table format descriptors. This is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the feature bit with an ID register check, in line with our preference for ID register checks over feature bits. Backports commit 0ae0326b984e77a55c224b7863071bd3d8951231		2021-03-01 19:06:15 -05:00
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arm	target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check	2021-03-01 19:06:15 -05:00
i386	i386/cpu: Clear FEAT_XSAVE_COMP_{LO,HI} when XSAVE is not available	2021-03-01 19:04:03 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Set instance_align on RISCVCPU TypeInfo	2021-03-01 19:00:27 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00