Rémi Denis-Courmont edd5f021e6 target/arm: add MMU stage 1 for Secure EL2 ... This adds the MMU indices for EL2 stage 1 in secure state. To keep code contained, which is largelly identical between secure and non-secure modes, the MMU indices are reassigned. The new assignments provide a systematic pattern with a non-secure bit. Backports b6ad6062f1e55bd5b9407ce89e55e3a08b83827c		2021-03-04 14:16:31 -05:00
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arm	target/arm: add MMU stage 1 for Secure EL2	2021-03-04 14:16:31 -05:00
i386	target/i386: Check privilege level for protected mode 'int N' task gate	2021-03-03 19:32:10 -05:00
m68k	m68k: fix some comment spelling errors	2021-03-03 19:13:26 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Set instance_align on RISCVCPU TypeInfo	2021-03-01 19:00:27 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00