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Yongbok Kim f10de71e73 target/mips: Amend CP0 WatchHi register implementation 
WatchHi is extended by the field MemoryMapID with the GINVT instruction.
The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/
DMFC0 in 64-bit architectures.

Backports commit feafe82cc2289a31b3e3f11dc76f3539ea22d670 from qemu
2020-03-21 12:39:00 -04:00
..
arm target/arm: Fix PAuth sbox functions 2020-03-21 12:17:26 -04:00
i386 target/i386: Add the 'model-id' for Skylake -v3 CPU models 2020-03-21 12:27:24 -04:00
m68k m68k: Fix regression causing Single-Step via GDB/RSP to not single step 2020-03-21 12:15:08 -04:00
mips target/mips: Amend CP0 WatchHi register implementation 2020-03-21 12:39:00 -04:00
riscv target/riscv: update mstatus.SD when FS is set dirty 2020-03-21 12:22:56 -04:00
sparc target/sparc: sun4u Invert Endian TTE bit 2020-01-07 19:21:30 -05:00