Richard Henderson f16dcbe226 target/arm: Rearrange Floating-point data-processing (2 regs) ... There are lots of special cases within these insns. Split the major argument decode/loading/saving into no_output (compares), rd_is_dp, and rm_is_dp. We still need to special case argument load for compare (rd as input, rm as zero) and vcvt fixed (rd as input+output), but lots of special cases do disappear. Now that we have a full switch at the beginning, hoist the ISA checks from the code generation. Backports commit e80941bd64cc388554770fd72334e9e7d459a1ef from qemu		2019-02-22 18:57:25 -05:00
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arm	target/arm: Rearrange Floating-point data-processing (2 regs)	2019-02-22 18:57:25 -05:00
i386	Revert "i386: Add CPUID bit for PCONFIG"	2019-02-07 08:56:40 -05:00
m68k	target/m68k: Fix LGPL information in the file headers	2019-02-03 17:55:29 -05:00
mips	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00