mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-24 13:05:37 +00:00
b6f752970b
This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
15 lines
450 B
C
15 lines
450 B
C
#ifndef HW_RISCV_SPIKE_H
|
|
#define HW_RISCV_SPIKE_H
|
|
|
|
#if defined(TARGET_RISCV32)
|
|
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
|
|
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
|
|
#elif defined(TARGET_RISCV64)
|
|
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
|
|
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
|
|
#endif
|
|
|
|
void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc);
|
|
|
|
#endif /* HW_RISCV_SPIKE_H */
|