Kito Cheng 5a7ad783e9 target/riscv: Fix wrong expanding for c.fswsp ... base register is no rs1 not rs2 for fsw. Backports commit 620455350a8da7cc62ae82cb69dd5c556f744136 from qemu		2019-03-26 20:39:34 -04:00
..
trans_privileged.inc.c	target/riscv: Convert RV priv insns to decodetree	2019-03-19 04:40:24 -04:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-18 16:27:53 -04:00
trans_rvc.inc.c	target/riscv: Fix wrong expanding for c.fswsp	2019-03-26 20:39:34 -04:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-18 16:43:17 -04:00
trans_rvi.inc.c	target/riscv: Rename trans_arith to gen_arith	2019-03-19 05:35:44 -04:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00