unicorn/qemu/target
Richard Henderson fd4ce2cba0 target/arm: Assert immh != 0 in disas_simd_shift_imm
Coverity raised a shed-load of errors cascading from inferring
that clz32(immh) might yield 32, from immh might be 0.

While immh cannot be 0 from encoding, it is not obvious even to
a human how we've checked that: via the filtering provided by
data_proc_simd[].

Backports commit 3944d58db3fc5bf131345a21a44013bc13849a12 from qemu
2020-04-30 06:53:54 -04:00
..
arm target/arm: Assert immh != 0 in disas_simd_shift_imm 2020-04-30 06:53:54 -04:00
i386 i386: Add 2nd Generation AMD EPYC processors 2020-04-30 06:50:02 -04:00
m68k m68k: Fix regression causing Single-Step via GDB/RSP to not single step 2020-03-21 12:15:08 -04:00
mips target/arm: fix TCG leak for fcvt half->double 2020-03-21 13:14:47 -04:00
riscv target/riscv: Fix VS mode interrupts forwarding. 2020-04-30 06:21:03 -04:00
sparc target/sparc: sun4u Invert Endian TTE bit 2020-01-07 19:21:30 -05:00