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ff7042567e
Convert the VFP load/store multiple insns to decodetree.
This includes tightening up the UNDEF checking for pre-VFPv3
CPUs which only have D0-D15 : they now UNDEF for any access
to D16-D31, not merely when the smallest register in the
transfer list is in D16-D31.
This conversion does not try to share code between the single
precision and the double precision versions; this looks a bit
duplicative of code, but it leaves the door open for a future
refactoring which gets rid of the use of the "F0" registers
by inlining the various functions like gen_vfp_ld() and
gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }"
conditionalisation.
Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
99 lines
3.7 KiB
Plaintext
99 lines
3.7 KiB
Plaintext
# AArch32 VFP instruction descriptions (conditional insns)
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#
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# Copyright (c) 2019 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# Encodings for the conditional VFP instructions are here:
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# generally anything matching A32
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# cccc 11.. .... .... .... 101. .... ....
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# and T32
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# 1110 110. .... .... .... 101. .... ....
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# 1110 1110 .... .... .... 101. .... ....
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# (but those patterns might also cover some Neon instructions,
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# which do not live in this file.)
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# VFP registers have an odd encoding with a four-bit field
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# and a one-bit field which are assembled in different orders
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# depending on whether the register is double or single precision.
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# Each individual instruction function must do the checks for
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# "double register selected but CPU does not have double support"
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# and "double register number has bit 4 set but CPU does not
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# support D16-D31" (which should UNDEF).
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%vm_dp 5:1 0:4
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%vm_sp 0:4 5:1
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%vn_dp 7:1 16:4
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%vn_sp 16:4 7:1
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%vd_dp 22:1 12:4
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%vd_sp 12:4 22:1
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%vmov_idx_b 21:1 5:2
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%vmov_idx_h 21:1 6:1
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# VMOV scalar to general-purpose register; note that this does
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# include some Neon cases.
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VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
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vn=%vn_dp size=0 index=%vmov_idx_b
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VMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \
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vn=%vn_dp size=1 index=%vmov_idx_h
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VMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \
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vn=%vn_dp size=2 u=0
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VMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \
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vn=%vn_dp size=0 index=%vmov_idx_b
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VMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \
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vn=%vn_dp size=1 index=%vmov_idx_h
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VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \
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vn=%vn_dp size=2
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VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
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vn=%vn_dp
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VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
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VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \
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vn=%vn_sp
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VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \
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vm=%vm_sp
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VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \
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vm=%vm_dp
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# Note that the half-precision variants of VLDR and VSTR are
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# not part of this decodetree at all because they have bits [9:8] == 0b01
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VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp
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VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp
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# We split the load/store multiple up into two patterns to avoid
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# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
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# grouping:
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# P=0 U=0 W=0 is 64-bit VMOV
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# P=1 W=0 is VLDR/VSTR
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# P=U W=1 is UNDEF
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# leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple.
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# These include FSTM/FLDM.
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VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp p=0 u=1
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VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp p=0 u=1
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VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp p=1 u=0 w=1
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VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp p=1 u=0 w=1
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