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https://github.com/yuzu-emu/yuzu-android.git
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Merge pull request #408 from bunnei/shader-ints-p2
gl_shader_decompiler: Add GLSLRegisterManager class to track register state.
This commit is contained in:
bunnei
GitHub
commit
6b365f7703
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@ -41,7 +41,7 @@ enum class ExitMethod {
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struct Subroutine {
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/// Generates a name suitable for GLSL source code.
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std::string GetName() const {
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return "sub_" + std::to_string(begin) + "_" + std::to_string(end);
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return "sub_" + std::to_string(begin) + '_' + std::to_string(end);
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}
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u32 begin; ///< Entry point of the subroutine.
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@ -216,6 +216,16 @@ public:
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return declr_type.find(Type::Integer) != declr_type.end();
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}
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/// Returns true if the active type is float
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bool IsFloat() const {
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return active_type == Type::Float;
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}
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/// Returns true if the active type is integer
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bool IsInteger() const {
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return active_type == Type::Integer;
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}
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private:
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enum class Type {
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Float,
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@ -230,41 +240,168 @@ private:
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std::set<Type> declr_type;
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};
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class GLSLGenerator {
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/**
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* Used to manage shader registers that are emulated with GLSL. This class keeps track of the state
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* of all registers (e.g. whether they are currently being used as Floats or Integers), and
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* generates the necessary GLSL code to perform conversions as needed. This class is used for
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* bookkeeping within the GLSL program.
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*/
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class GLSLRegisterManager {
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public:
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GLSLGenerator(const std::set<Subroutine>& subroutines, const ProgramCode& program_code,
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u32 main_offset, Maxwell3D::Regs::ShaderStage stage)
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: subroutines(subroutines), program_code(program_code), main_offset(main_offset),
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stage(stage) {
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GLSLRegisterManager(ShaderWriter& shader, ShaderWriter& declarations,
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const Maxwell3D::Regs::ShaderStage& stage)
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: shader{shader}, declarations{declarations}, stage{stage} {
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BuildRegisterList();
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Generate();
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}
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std::string GetShaderCode() {
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return declarations.GetResult() + shader.GetResult();
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/// Generates code representing a temporary (GPR) register.
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (reg == Register::ZeroIndex) {
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return "0";
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}
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return regs[reg.GetSwizzledIndex(elem)].GetActiveString();
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}
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/// Returns entries in the shader that are useful for external functions
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ShaderEntries GetEntries() const {
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return {GetConstBuffersDeclarations()};
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/**
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* Writes code that does a register assignment to float value operation. Should only be used
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* with shader instructions that deal with floats.
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* @param reg The destination register to use.
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* @param elem The element to use for the operation.
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* @param value The code representing the value to assign.
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* @param dest_num_components Number of components in the destination.
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* @param value_num_components Number of components in the value.
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* @param is_abs Optional, when True, applies absolute value to output.
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* @param dest_elem Optional, the destination element to use for the operation.
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*/
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void SetRegisterToFloat(const Register& reg, u64 elem, const std::string& value,
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u64 dest_num_components, u64 value_num_components, bool is_abs = false,
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u64 dest_elem = 0) {
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ASSERT(regs[reg].IsFloat());
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std::string dest = GetRegister(reg, dest_elem);
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if (dest_num_components > 1) {
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dest += GetSwizzle(elem);
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}
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std::string src = '(' + value + ')';
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if (value_num_components > 1) {
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src += GetSwizzle(elem);
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}
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src = is_abs ? "abs(" + src + ')' : src;
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shader.AddLine(dest + " = " + src + ';');
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}
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/**
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* Writes code that does a register assignment to input attribute operation. Input attributes
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* are stored as floats, so this may require conversion.
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* @param reg The destination register to use.
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* @param elem The element to use for the operation.
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* @param attribute The input attibute to use as the source value.
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*/
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void SetRegisterToInputAttibute(const Register& reg, u64 elem, Attribute::Index attribute) {
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std::string dest = GetRegister(reg);
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std::string src = GetInputAttribute(attribute) + GetSwizzle(elem);
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if (regs[reg].IsFloat()) {
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shader.AddLine(dest + " = " + src + ';');
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} else if (regs[reg].IsInteger()) {
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shader.AddLine(dest + " = floatBitsToInt(" + src + ");");
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} else {
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UNREACHABLE();
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}
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}
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/**
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* Writes code that does a output attribute assignment to register operation. Output attributes
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* are stored as floats, so this may require conversion.
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* @param attribute The destination output attribute.
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* @param elem The element to use for the operation.
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* @param reg The register to use as the source value.
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*/
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void SetOutputAttributeToRegister(Attribute::Index attribute, u64 elem, const Register& reg) {
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std::string dest = GetOutputAttribute(attribute) + GetSwizzle(elem);
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std::string src = GetRegister(reg);
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ASSERT_MSG(regs[reg].IsFloat(), "Output attributes must be set to a float");
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shader.AddLine(dest + " = " + src + ';');
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}
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/// Generates code representing a uniform (C buffer) register.
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std::string GetUniform(const Uniform& uniform, const Register& dest_reg) {
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declr_const_buffers[uniform.index].MarkAsUsed(static_cast<unsigned>(uniform.index),
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static_cast<unsigned>(uniform.offset), stage);
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std::string value =
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'c' + std::to_string(uniform.index) + '[' + std::to_string(uniform.offset) + ']';
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if (regs[dest_reg].IsFloat()) {
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return value;
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} else if (regs[dest_reg].IsInteger()) {
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return "floatBitsToInt(" + value + ')';
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} else {
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UNREACHABLE();
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}
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}
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/// Add declarations for registers
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void GenerateDeclarations() {
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for (const auto& reg : regs) {
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if (reg.IsFloatUsed()) {
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declarations.AddLine("float " + reg.GetFloatString() + " = 0.0;");
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}
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if (reg.IsIntegerUsed()) {
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declarations.AddLine("int " + reg.GetIntegerString() + " = 0;");
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}
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}
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declarations.AddNewLine();
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for (const auto& index : declr_input_attribute) {
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// TODO(bunnei): Use proper number of elements for these
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declarations.AddLine("layout(location = " +
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std::to_string(static_cast<u32>(index) -
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static_cast<u32>(Attribute::Index::Attribute_0)) +
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") in vec4 " + GetInputAttribute(index) + ';');
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}
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declarations.AddNewLine();
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for (const auto& index : declr_output_attribute) {
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// TODO(bunnei): Use proper number of elements for these
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declarations.AddLine("layout(location = " +
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std::to_string(static_cast<u32>(index) -
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static_cast<u32>(Attribute::Index::Attribute_0)) +
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") out vec4 " + GetOutputAttribute(index) + ';');
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}
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declarations.AddNewLine();
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unsigned const_buffer_layout = 0;
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for (const auto& entry : GetConstBuffersDeclarations()) {
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declarations.AddLine("layout(std430) buffer " + entry.GetName());
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declarations.AddLine('{');
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declarations.AddLine(" float c" + std::to_string(entry.GetIndex()) + "[];");
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declarations.AddLine("};");
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declarations.AddNewLine();
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++const_buffer_layout;
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}
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declarations.AddNewLine();
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}
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/// Returns a list of constant buffer declarations
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std::vector<ConstBufferEntry> GetConstBuffersDeclarations() const {
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std::vector<ConstBufferEntry> result;
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std::copy_if(declr_const_buffers.begin(), declr_const_buffers.end(),
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std::back_inserter(result), [](const auto& entry) { return entry.IsUsed(); });
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return result;
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}
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private:
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/// Build the GLSL register list
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/// Build the GLSL register list.
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void BuildRegisterList() {
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for (size_t index = 0; index < Register::NumRegisters; ++index) {
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regs.emplace_back(index, shader);
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}
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}
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/// Gets the Subroutine object corresponding to the specified address.
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const Subroutine& GetSubroutine(u32 begin, u32 end) const {
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auto iter = subroutines.find(Subroutine{begin, end});
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ASSERT(iter != subroutines.end());
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return *iter;
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}
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/// Generates code representing an input attribute register.
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std::string GetInputAttribute(Attribute::Index attribute) {
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switch (attribute) {
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@ -301,6 +438,50 @@ private:
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}
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}
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/// Generates code to use for a swizzle operation.
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static std::string GetSwizzle(u64 elem) {
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ASSERT(elem <= 3);
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std::string swizzle = ".";
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swizzle += "xyzw"[elem];
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return swizzle;
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}
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ShaderWriter& shader;
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ShaderWriter& declarations;
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std::vector<GLSLRegister> regs;
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std::set<Attribute::Index> declr_input_attribute;
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std::set<Attribute::Index> declr_output_attribute;
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std::array<ConstBufferEntry, Maxwell3D::Regs::MaxConstBuffers> declr_const_buffers;
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const Maxwell3D::Regs::ShaderStage& stage;
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};
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class GLSLGenerator {
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public:
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GLSLGenerator(const std::set<Subroutine>& subroutines, const ProgramCode& program_code,
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u32 main_offset, Maxwell3D::Regs::ShaderStage stage)
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: subroutines(subroutines), program_code(program_code), main_offset(main_offset),
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stage(stage) {
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Generate();
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}
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std::string GetShaderCode() {
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return declarations.GetResult() + shader.GetResult();
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}
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/// Returns entries in the shader that are useful for external functions
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ShaderEntries GetEntries() const {
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return {regs.GetConstBuffersDeclarations()};
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}
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private:
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/// Gets the Subroutine object corresponding to the specified address.
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const Subroutine& GetSubroutine(u32 begin, u32 end) const {
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auto iter = subroutines.find(Subroutine{begin, end});
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ASSERT(iter != subroutines.end());
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return *iter;
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}
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/// Generates code representing a 19-bit immediate value
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static std::string GetImmediate19(const Instruction& instr) {
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return std::to_string(instr.alu.GetImm20_19());
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@ -311,29 +492,13 @@ private:
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return std::to_string(instr.alu.GetImm20_32());
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}
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/// Generates code representing a temporary (GPR) register.
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (reg == Register::ZeroIndex) {
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return "0";
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}
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return regs[reg.GetSwizzledIndex(elem)].GetActiveString();
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}
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/// Generates code representing a uniform (C buffer) register.
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std::string GetUniform(const Uniform& reg) {
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declr_const_buffers[reg.index].MarkAsUsed(static_cast<unsigned>(reg.index),
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static_cast<unsigned>(reg.offset), stage);
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return 'c' + std::to_string(reg.index) + '[' + std::to_string(reg.offset) + ']';
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}
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/// Generates code representing a texture sampler.
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std::string GetSampler(const Sampler& sampler) const {
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// TODO(Subv): Support more than just texture sampler 0
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ASSERT_MSG(sampler.index == Sampler::Index::Sampler_0, "unsupported");
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const unsigned index{static_cast<unsigned>(sampler.index.Value()) -
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static_cast<unsigned>(Sampler::Index::Sampler_0)};
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return "tex[" + std::to_string(index) + "]";
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return "tex[" + std::to_string(index) + ']';
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}
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/**
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@ -351,23 +516,6 @@ private:
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}
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}
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/**
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* Writes code that does an assignment operation.
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* @param reg the destination register code.
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* @param value the code representing the value to assign.
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*/
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void SetDest(u64 elem, const std::string& reg, const std::string& value,
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u64 dest_num_components, u64 value_num_components, bool is_abs = false) {
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std::string swizzle = ".";
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swizzle += "xyzw"[elem];
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std::string dest = reg + (dest_num_components != 1 ? swizzle : "");
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std::string src = "(" + value + ")" + (value_num_components != 1 ? swizzle : "");
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src = is_abs ? "abs(" + src + ")" : src;
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shader.AddLine(dest + " = " + src + ";");
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}
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/*
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* Writes code that assigns a predicate boolean variable.
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* @param pred The id of the predicate to write to.
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@ -449,11 +597,10 @@ private:
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switch (opcode->GetType()) {
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case OpCode::Type::Arithmetic: {
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = instr.alu.negate_a ? "-" : "";
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op_a += GetRegister(instr.gpr8);
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op_a += regs.GetRegister(instr.gpr8);
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if (instr.alu.abs_a) {
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op_a = "abs(" + op_a + ")";
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op_a = "abs(" + op_a + ')';
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}
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std::string op_b = instr.alu.negate_b ? "-" : "";
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@ -462,56 +609,64 @@ private:
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op_b += GetImmediate19(instr);
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} else {
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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op_b += regs.GetRegister(instr.gpr20);
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} else {
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op_b += GetUniform(instr.uniform);
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op_b += regs.GetUniform(instr.uniform, instr.gpr0);
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}
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}
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if (instr.alu.abs_b) {
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op_b = "abs(" + op_b + ")";
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op_b = "abs(" + op_b + ')';
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}
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switch (opcode->GetId()) {
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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SetDest(0, dest, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
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break;
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}
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case OpCode::Id::FMUL32_IMM: {
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// fmul32i doesn't have abs or neg bits.
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SetDest(0, dest, GetRegister(instr.gpr8) + " * " + GetImmediate32(instr), 1, 1);
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regs.SetRegisterToFloat(
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instr.gpr0, 0, regs.GetRegister(instr.gpr8) + " * " + GetImmediate32(instr), 1,
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1);
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break;
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}
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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SetDest(0, dest, op_a + " + " + op_b, 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1, instr.alu.abs_d);
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break;
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}
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case OpCode::Id::MUFU: {
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switch (instr.sub_op) {
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case SubOp::Cos:
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SetDest(0, dest, "cos(" + op_a + ")", 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, "cos(" + op_a + ')', 1, 1,
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instr.alu.abs_d);
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break;
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case SubOp::Sin:
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SetDest(0, dest, "sin(" + op_a + ")", 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, "sin(" + op_a + ')', 1, 1,
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instr.alu.abs_d);
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break;
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case SubOp::Ex2:
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SetDest(0, dest, "exp2(" + op_a + ")", 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, "exp2(" + op_a + ')', 1, 1,
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instr.alu.abs_d);
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break;
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case SubOp::Lg2:
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SetDest(0, dest, "log2(" + op_a + ")", 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, "log2(" + op_a + ')', 1, 1,
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instr.alu.abs_d);
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break;
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case SubOp::Rcp:
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SetDest(0, dest, "1.0 / " + op_a, 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, "1.0 / " + op_a, 1, 1, instr.alu.abs_d);
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break;
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case SubOp::Rsq:
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SetDest(0, dest, "inversesqrt(" + op_a + ")", 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, "inversesqrt(" + op_a + ')', 1, 1,
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instr.alu.abs_d);
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break;
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case SubOp::Min:
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SetDest(0, dest, "min(" + op_a + "," + op_b + ")", 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, "min(" + op_a + "," + op_b + ')', 1, 1,
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instr.alu.abs_d);
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break;
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default:
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NGLOG_CRITICAL(HW_GPU, "Unhandled MUFU sub op: {0:x}",
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@ -532,30 +687,29 @@ private:
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break;
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}
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case OpCode::Type::Ffma: {
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = GetRegister(instr.gpr8);
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std::string op_a = regs.GetRegister(instr.gpr8);
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std::string op_b = instr.ffma.negate_b ? "-" : "";
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std::string op_c = instr.ffma.negate_c ? "-" : "";
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|
||||
switch (opcode->GetId()) {
|
||||
case OpCode::Id::FFMA_CR: {
|
||||
op_b += GetUniform(instr.uniform);
|
||||
op_c += GetRegister(instr.gpr39);
|
||||
op_b += regs.GetUniform(instr.uniform, instr.gpr0);
|
||||
op_c += regs.GetRegister(instr.gpr39);
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::FFMA_RR: {
|
||||
op_b += GetRegister(instr.gpr20);
|
||||
op_c += GetRegister(instr.gpr39);
|
||||
op_b += regs.GetRegister(instr.gpr20);
|
||||
op_c += regs.GetRegister(instr.gpr39);
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::FFMA_RC: {
|
||||
op_b += GetRegister(instr.gpr39);
|
||||
op_c += GetUniform(instr.uniform);
|
||||
op_b += regs.GetRegister(instr.gpr39);
|
||||
op_c += regs.GetUniform(instr.uniform, instr.gpr0);
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::FFMA_IMM: {
|
||||
op_b += GetImmediate19(instr);
|
||||
op_c += GetRegister(instr.gpr39);
|
||||
op_c += regs.GetRegister(instr.gpr39);
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
|
|
@ -564,28 +718,29 @@ private:
|
|||
}
|
||||
}
|
||||
|
||||
SetDest(0, dest, op_a + " * " + op_b + " + " + op_c, 1, 1);
|
||||
regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b + " + " + op_c, 1, 1);
|
||||
break;
|
||||
}
|
||||
case OpCode::Type::Memory: {
|
||||
std::string gpr0 = GetRegister(instr.gpr0);
|
||||
const Attribute::Index attribute = instr.attribute.fmt20.index;
|
||||
|
||||
switch (opcode->GetId()) {
|
||||
case OpCode::Id::LD_A: {
|
||||
ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
|
||||
SetDest(instr.attribute.fmt20.element, gpr0, GetInputAttribute(attribute), 1, 4);
|
||||
regs.SetRegisterToInputAttibute(instr.gpr0, instr.attribute.fmt20.element,
|
||||
attribute);
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::ST_A: {
|
||||
ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
|
||||
SetDest(instr.attribute.fmt20.element, GetOutputAttribute(attribute), gpr0, 4, 1);
|
||||
regs.SetOutputAttributeToRegister(attribute, instr.attribute.fmt20.element,
|
||||
instr.gpr0);
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::TEXS: {
|
||||
ASSERT_MSG(instr.attribute.fmt20.size == 4, "untested");
|
||||
const std::string op_a = GetRegister(instr.gpr8);
|
||||
const std::string op_b = GetRegister(instr.gpr20);
|
||||
const std::string op_a = regs.GetRegister(instr.gpr8);
|
||||
const std::string op_b = regs.GetRegister(instr.gpr20);
|
||||
const std::string sampler = GetSampler(instr.sampler);
|
||||
const std::string coord = "vec2 coords = vec2(" + op_a + ", " + op_b + ");";
|
||||
// Add an extra scope and declare the texture coords inside to prevent overwriting
|
||||
|
|
@ -595,7 +750,7 @@ private:
|
|||
shader.AddLine(coord);
|
||||
const std::string texture = "texture(" + sampler + ", coords)";
|
||||
for (unsigned elem = 0; elem < instr.attribute.fmt20.size; ++elem) {
|
||||
SetDest(elem, GetRegister(instr.gpr0, elem), texture, 1, 4);
|
||||
regs.SetRegisterToFloat(instr.gpr0, elem, texture, 1, 4, false, elem);
|
||||
}
|
||||
--shader.scope;
|
||||
shader.AddLine("}");
|
||||
|
|
@ -610,7 +765,7 @@ private:
|
|||
}
|
||||
case OpCode::Type::FloatSetPredicate: {
|
||||
std::string op_a = instr.fsetp.neg_a ? "-" : "";
|
||||
op_a += GetRegister(instr.gpr8);
|
||||
op_a += regs.GetRegister(instr.gpr8);
|
||||
|
||||
if (instr.fsetp.abs_a) {
|
||||
op_a = "abs(" + op_a + ')';
|
||||
|
|
@ -626,9 +781,9 @@ private:
|
|||
op_b += '(' + GetImmediate19(instr) + ')';
|
||||
} else {
|
||||
if (instr.is_b_gpr) {
|
||||
op_b += GetRegister(instr.gpr20);
|
||||
op_b += regs.GetRegister(instr.gpr20);
|
||||
} else {
|
||||
op_b += GetUniform(instr.uniform);
|
||||
op_b += regs.GetUniform(instr.uniform, instr.gpr0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -660,9 +815,8 @@ private:
|
|||
break;
|
||||
}
|
||||
case OpCode::Type::FloatSet: {
|
||||
std::string dest = GetRegister(instr.gpr0);
|
||||
std::string op_a = instr.fset.neg_a ? "-" : "";
|
||||
op_a += GetRegister(instr.gpr8);
|
||||
op_a += regs.GetRegister(instr.gpr8);
|
||||
|
||||
if (instr.fset.abs_a) {
|
||||
op_a = "abs(" + op_a + ')';
|
||||
|
|
@ -678,14 +832,14 @@ private:
|
|||
op_b += imm;
|
||||
} else {
|
||||
if (instr.is_b_gpr) {
|
||||
op_b += GetRegister(instr.gpr20);
|
||||
op_b += regs.GetRegister(instr.gpr20);
|
||||
} else {
|
||||
op_b += GetUniform(instr.uniform);
|
||||
op_b += regs.GetUniform(instr.uniform, instr.gpr0);
|
||||
}
|
||||
}
|
||||
|
||||
if (instr.fset.abs_b) {
|
||||
op_b = "abs(" + op_b + ")";
|
||||
op_b = "abs(" + op_b + ')';
|
||||
}
|
||||
|
||||
using Tegra::Shader::Pred;
|
||||
|
|
@ -697,13 +851,16 @@ private:
|
|||
using Tegra::Shader::PredCondition;
|
||||
switch (instr.fset.cond) {
|
||||
case PredCondition::LessThan:
|
||||
SetDest(0, dest, "((" + op_a + ") < (" + op_b + ")) ? 1.0 : 0", 1, 1);
|
||||
regs.SetRegisterToFloat(instr.gpr0, 0,
|
||||
"((" + op_a + ") < (" + op_b + ")) ? 1.0 : 0", 1, 1);
|
||||
break;
|
||||
case PredCondition::Equal:
|
||||
SetDest(0, dest, "((" + op_a + ") == (" + op_b + ")) ? 1.0 : 0", 1, 1);
|
||||
regs.SetRegisterToFloat(instr.gpr0, 0,
|
||||
"((" + op_a + ") == (" + op_b + ")) ? 1.0 : 0", 1, 1);
|
||||
break;
|
||||
case PredCondition::GreaterThan:
|
||||
SetDest(0, dest, "((" + op_a + ") > (" + op_b + ")) ? 1.0 : 0", 1, 1);
|
||||
regs.SetRegisterToFloat(instr.gpr0, 0,
|
||||
"((" + op_a + ") > (" + op_b + ")) ? 1.0 : 0", 1, 1);
|
||||
break;
|
||||
default:
|
||||
NGLOG_CRITICAL(HW_GPU, "Unhandled predicate condition: {} (a: {}, b: {})",
|
||||
|
|
@ -720,10 +877,10 @@ private:
|
|||
|
||||
// Final color output is currently hardcoded to GPR0-3 for fragment shaders
|
||||
if (stage == Maxwell3D::Regs::ShaderStage::Fragment) {
|
||||
shader.AddLine("color.r = " + GetRegister(0) + ";");
|
||||
shader.AddLine("color.g = " + GetRegister(1) + ";");
|
||||
shader.AddLine("color.b = " + GetRegister(2) + ";");
|
||||
shader.AddLine("color.a = " + GetRegister(3) + ";");
|
||||
shader.AddLine("color.r = " + regs.GetRegister(0) + ';');
|
||||
shader.AddLine("color.g = " + regs.GetRegister(1) + ';');
|
||||
shader.AddLine("color.b = " + regs.GetRegister(2) + ';');
|
||||
shader.AddLine("color.a = " + regs.GetRegister(3) + ';');
|
||||
}
|
||||
|
||||
shader.AddLine("return true;");
|
||||
|
|
@ -736,8 +893,7 @@ private:
|
|||
}
|
||||
case OpCode::Id::IPA: {
|
||||
const auto& attribute = instr.attribute.fmt28;
|
||||
std::string dest = GetRegister(instr.gpr0);
|
||||
SetDest(attribute.element, dest, GetInputAttribute(attribute.index), 1, 4);
|
||||
regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index);
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
|
|
@ -843,55 +999,10 @@ private:
|
|||
GenerateDeclarations();
|
||||
}
|
||||
|
||||
/// Returns a list of constant buffer declarations
|
||||
std::vector<ConstBufferEntry> GetConstBuffersDeclarations() const {
|
||||
std::vector<ConstBufferEntry> result;
|
||||
std::copy_if(declr_const_buffers.begin(), declr_const_buffers.end(),
|
||||
std::back_inserter(result), [](const auto& entry) { return entry.IsUsed(); });
|
||||
return result;
|
||||
}
|
||||
|
||||
/// Add declarations for registers
|
||||
void GenerateDeclarations() {
|
||||
for (const auto& reg : regs) {
|
||||
if (reg.IsFloatUsed()) {
|
||||
declarations.AddLine("float " + reg.GetFloatString() + " = 0.0;");
|
||||
}
|
||||
if (reg.IsIntegerUsed()) {
|
||||
declarations.AddLine("int " + reg.GetIntegerString() + " = 0;");
|
||||
}
|
||||
}
|
||||
declarations.AddNewLine();
|
||||
regs.GenerateDeclarations();
|
||||
|
||||
for (const auto& index : declr_input_attribute) {
|
||||
// TODO(bunnei): Use proper number of elements for these
|
||||
declarations.AddLine("layout(location = " +
|
||||
std::to_string(static_cast<u32>(index) -
|
||||
static_cast<u32>(Attribute::Index::Attribute_0)) +
|
||||
") in vec4 " + GetInputAttribute(index) + ";");
|
||||
}
|
||||
declarations.AddNewLine();
|
||||
|
||||
for (const auto& index : declr_output_attribute) {
|
||||
// TODO(bunnei): Use proper number of elements for these
|
||||
declarations.AddLine("layout(location = " +
|
||||
std::to_string(static_cast<u32>(index) -
|
||||
static_cast<u32>(Attribute::Index::Attribute_0)) +
|
||||
") out vec4 " + GetOutputAttribute(index) + ";");
|
||||
}
|
||||
declarations.AddNewLine();
|
||||
|
||||
unsigned const_buffer_layout = 0;
|
||||
for (const auto& entry : GetConstBuffersDeclarations()) {
|
||||
declarations.AddLine("layout(std430) buffer " + entry.GetName());
|
||||
declarations.AddLine('{');
|
||||
declarations.AddLine(" float c" + std::to_string(entry.GetIndex()) + "[];");
|
||||
declarations.AddLine("};");
|
||||
declarations.AddNewLine();
|
||||
++const_buffer_layout;
|
||||
}
|
||||
|
||||
declarations.AddNewLine();
|
||||
for (const auto& pred : declr_predicates) {
|
||||
declarations.AddLine("bool " + pred + " = false;");
|
||||
}
|
||||
|
|
@ -906,13 +1017,10 @@ private:
|
|||
|
||||
ShaderWriter shader;
|
||||
ShaderWriter declarations;
|
||||
std::vector<GLSLRegister> regs;
|
||||
GLSLRegisterManager regs{shader, declarations, stage};
|
||||
|
||||
// Declarations
|
||||
std::set<std::string> declr_predicates;
|
||||
std::set<Attribute::Index> declr_input_attribute;
|
||||
std::set<Attribute::Index> declr_output_attribute;
|
||||
std::array<ConstBufferEntry, Maxwell3D::Regs::MaxConstBuffers> declr_const_buffers;
|
||||
}; // namespace Decompiler
|
||||
|
||||
std::string GetCommonDeclarations() {
|
||||
|
|
|
|||
Loading…
Reference in a new issue