mirror of
https://github.com/yuzu-emu/yuzu-mainline.git
synced 2024-12-23 16:55:36 +00:00
SMMU: Implement physical memory mirroring
This commit is contained in:
parent
0a2536a0df
commit
34a8d0cc8e
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@ -10,8 +10,10 @@
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#include <mutex>
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#include "common/common_types.h"
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#include "common/scratch_buffer.h"
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#include "common/virtual_buffer.h"
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namespace Core {
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class DeviceMemory;
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@ -49,9 +51,25 @@ public:
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template <typename T>
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const T* GetPointer(DAddr address) const;
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DAddr GetAddressFromPAddr(PAddr address) const {
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template <typename Func>
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void ApplyOpOnPAddr(PAddr address, Common::ScratchBuffer<u32>& buffer, Func&& operation) {
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DAddr subbits = static_cast<DAddr>(address & page_mask);
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return (static_cast<DAddr>(compressed_device_addr[(address >> page_bits)]) << page_bits) + subbits;
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const u32 base = compressed_device_addr[(address >> page_bits)];
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if ((base >> MULTI_FLAG_BITS) == 0) [[likely]] {
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const DAddr d_address = static_cast<DAddr>(base << page_bits) + subbits;
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operation(d_address);
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return;
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}
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InnerGatherDeviceAddresses(buffer, address);
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for (u32 value : buffer) {
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operation(static_cast<DAddr>(value << page_bits) + subbits);
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}
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}
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template <typename Func>
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void ApplyOpOnPointer(const u8* p, Common::ScratchBuffer<u32>& buffer, Func&& operation) {
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PAddr address = GetRawPhysicalAddr<u8>(p);
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ApplyOpOnPAddr(address, buffer, operation);
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}
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PAddr GetPhysicalRawAddressFromDAddr(DAddr address) const {
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@ -98,6 +116,9 @@ private:
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static constexpr size_t page_size = 1ULL << page_bits;
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static constexpr size_t page_mask = page_size - 1ULL;
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static constexpr u32 physical_address_base = 1U << page_bits;
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static constexpr u32 MULTI_FLAG_BITS = 31;
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static constexpr u32 MULTI_FLAG = 1U << MULTI_FLAG_BITS;
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static constexpr u32 MULTI_MASK = ~MULTI_FLAG;
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template <typename T>
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T* GetPointerFromRaw(PAddr addr) {
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@ -117,6 +138,8 @@ private:
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void WalkBlock(const DAddr addr, const std::size_t size, auto on_unmapped, auto on_memory,
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auto increment);
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void InnerGatherDeviceAddresses(Common::ScratchBuffer<u32>& buffer, PAddr address);
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std::unique_ptr<DeviceMemoryManagerAllocator<Traits>> impl;
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const uintptr_t physical_base;
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@ -18,10 +18,117 @@
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namespace Core {
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namespace {
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class PhysicalAddressContainer {
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public:
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PhysicalAddressContainer() = default;
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~PhysicalAddressContainer() = default;
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void GatherValues(u32 start_entry, Common::ScratchBuffer<u32>& buffer) {
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buffer.resize(8);
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buffer.resize(0);
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size_t index = 0;
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const auto add_value = [&](u32 value) {
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buffer[index] = value;
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index++;
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buffer.resize(index);
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};
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u32 iter_entry = start_entry;
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Entry* current = &storage[iter_entry - 1];
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add_value(current->value);
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while (current->next_entry != 0) {
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iter_entry = current->next_entry;
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current = &storage[iter_entry - 1];
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add_value(current->value);
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}
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}
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u32 Register(u32 value) {
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return RegisterImplementation(value);
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}
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void Register(u32 value, u32 start_entry) {
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auto entry_id = RegisterImplementation(value);
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u32 iter_entry = start_entry;
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Entry* current = &storage[iter_entry - 1];
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while (current->next_entry != 0) {
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iter_entry = current->next_entry;
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current = &storage[iter_entry - 1];
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}
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current->next_entry = entry_id;
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}
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std::pair<bool, u32> Unregister(u32 value, u32 start_entry) {
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u32 iter_entry = start_entry;
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Entry* previous{};
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Entry* current = &storage[iter_entry - 1];
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Entry* next{};
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bool more_than_one_remaining = false;
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u32 result_start{start_entry};
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size_t count = 0;
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while (current->value != value) {
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count++;
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previous = current;
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iter_entry = current->next_entry;
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current = &storage[iter_entry - 1];
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}
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// Find next
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u32 next_entry = current->next_entry;
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if (next_entry != 0) {
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next = &storage[next_entry - 1];
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more_than_one_remaining = next->next_entry != 0;
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}
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if (previous) {
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previous->next_entry = next_entry;
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} else {
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result_start = next_entry;
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}
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free_entries.emplace_back(iter_entry);
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return std::make_pair(more_than_one_remaining || count > 1, result_start);
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}
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u32 ReleaseEntry(u32 start_entry) {
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Entry* current = &storage[start_entry - 1];
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free_entries.emplace_back(start_entry);
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return current->value;
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}
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private:
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u32 RegisterImplementation(u32 value) {
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auto entry_id = GetNewEntry();
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auto& entry = storage[entry_id - 1];
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entry.next_entry = 0;
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entry.value = value;
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return entry_id;
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}
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u32 GetNewEntry() {
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if (!free_entries.empty()) {
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u32 result = free_entries.front();
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free_entries.pop_front();
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return result;
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}
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storage.emplace_back();
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u32 new_entry = static_cast<u32>(storage.size());
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return new_entry;
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}
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struct Entry {
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u32 next_entry{};
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u32 value{};
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};
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std::deque<Entry> storage;
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std::deque<u32> free_entries;
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};
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struct EmptyAllocator {
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EmptyAllocator([[maybe_unused]] DAddr address) {}
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};
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} // namespace
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template <typename DTraits>
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struct DeviceMemoryManagerAllocator {
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static constexpr bool supports_pinning = DTraits::supports_pinning;
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@ -38,6 +145,7 @@ struct DeviceMemoryManagerAllocator {
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std::conditional_t<supports_pinning, Common::FlatAllocator<DAddr, 0, pin_bits>, EmptyAllocator>
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pin_allocator;
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Common::FlatAllocator<DAddr, 0, device_virtual_bits> main_allocator;
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PhysicalAddressContainer multi_dev_address;
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/// Returns true when vaddr -> vaddr+size is fully contained in the buffer
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template <bool pin_area>
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@ -109,6 +217,9 @@ DeviceMemoryManager<Traits>::DeviceMemoryManager(const DeviceMemory& device_memo
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cpu_backing_address(device_as_size >> Memory::YUZU_PAGEBITS) {
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impl = std::make_unique<DeviceMemoryManagerAllocator<Traits>>();
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cached_pages = std::make_unique<CachedPages>();
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for (size_t i = 0; i < 1ULL << (33 - 12); i++) {
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compressed_device_addr[i] = 0;
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}
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}
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template <typename Traits>
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@ -155,8 +266,19 @@ void DeviceMemoryManager<Traits>::Map(DAddr address, VAddr virtual_address, size
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}
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auto phys_addr = static_cast<u32>(GetRawPhysicalAddr(ptr) >> Memory::YUZU_PAGEBITS) + 1U;
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compressed_physical_ptr[start_page_d + i] = phys_addr;
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compressed_device_addr[phys_addr - 1U] = static_cast<u32>(start_page_d + i);
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InsertCPUBacking(start_page_d + i, new_vaddress, process_id);
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const u32 base_dev = compressed_device_addr[phys_addr - 1U];
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const u32 new_dev = static_cast<u32>(start_page_d + i);
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if (base_dev == 0) [[likely]] {
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compressed_device_addr[phys_addr - 1U] = new_dev;
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continue;
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}
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u32 start_id = base_dev & MULTI_MASK;
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if ((base_dev >> MULTI_FLAG_BITS) == 0) {
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start_id = impl->multi_dev_address.Register(base_dev);
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compressed_device_addr[phys_addr - 1U] = MULTI_FLAG | start_id;
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}
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impl->multi_dev_address.Register(new_dev, start_id);
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}
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}
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@ -170,12 +292,38 @@ void DeviceMemoryManager<Traits>::Unmap(DAddr address, size_t size) {
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auto phys_addr = compressed_physical_ptr[start_page_d + i];
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compressed_physical_ptr[start_page_d + i] = 0;
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cpu_backing_address[start_page_d + i] = 0;
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if (phys_addr != 0) {
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if (phys_addr != 0) [[likely]] {
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const u32 base_dev = compressed_device_addr[phys_addr - 1U];
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if ((base_dev >> MULTI_FLAG_BITS) == 0) [[likely]] {
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compressed_device_addr[phys_addr - 1] = 0;
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continue;
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}
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const auto [more_entries, new_start] = impl->multi_dev_address.Unregister(
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static_cast<u32>(start_page_d + i), base_dev & MULTI_MASK);
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if (!more_entries) {
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compressed_device_addr[phys_addr - 1] =
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impl->multi_dev_address.ReleaseEntry(new_start);
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continue;
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}
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compressed_device_addr[phys_addr - 1] = new_start | MULTI_FLAG;
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}
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}
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}
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template <typename Traits>
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void DeviceMemoryManager<Traits>::InnerGatherDeviceAddresses(Common::ScratchBuffer<u32>& buffer,
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PAddr address) {
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size_t phys_addr = address >> page_bits;
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std::scoped_lock lk(mapping_guard);
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u32 backing = compressed_device_addr[phys_addr];
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if ((backing >> MULTI_FLAG_BITS) != 0) {
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impl->multi_dev_address.GatherValues(backing & MULTI_MASK, buffer);
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return;
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}
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buffer.resize(1);
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buffer[0] = backing;
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}
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template <typename Traits>
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template <typename T>
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T* DeviceMemoryManager<Traits>::GetPointer(DAddr address) {
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@ -16,8 +16,8 @@
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namespace Service::Nvidia::NvCore {
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struct ContainerImpl {
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explicit ContainerImpl(Tegra::Host1x::Host1x& host1x_)
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: host1x{host1x_}, file{host1x_}, manager{host1x_}, device_file_data{} {}
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explicit ContainerImpl(Container& core, Tegra::Host1x::Host1x& host1x_)
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: host1x{host1x_}, file{core, host1x_}, manager{host1x_}, device_file_data{} {}
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Tegra::Host1x::Host1x& host1x;
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NvMap file;
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SyncpointManager manager;
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};
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Container::Container(Tegra::Host1x::Host1x& host1x_) {
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impl = std::make_unique<ContainerImpl>(host1x_);
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impl = std::make_unique<ContainerImpl>(*this, host1x_);
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}
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Container::~Container() = default;
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@ -7,6 +7,7 @@
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "core/hle/service/nvdrv/core/container.h"
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#include "core/hle/service/nvdrv/core/nvmap.h"
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#include "core/memory.h"
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#include "video_core/host1x/host1x.h"
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@ -64,7 +65,7 @@ NvResult NvMap::Handle::Duplicate(bool internal_session) {
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return NvResult::Success;
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}
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NvMap::NvMap(Tegra::Host1x::Host1x& host1x_) : host1x{host1x_} {}
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NvMap::NvMap(Container& core_, Tegra::Host1x::Host1x& host1x_) : host1x{host1x_}, core{core_} {}
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void NvMap::AddHandle(std::shared_ptr<Handle> handle_description) {
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std::scoped_lock lock(handles_lock);
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@ -160,6 +161,8 @@ DAddr NvMap::PinHandle(NvMap::Handle::Id handle, size_t session_id, bool low_are
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// If not then allocate some space and map it
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DAddr address{};
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auto& smmu = host1x.MemoryManager();
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auto* session = core.GetSession(session_id);
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auto allocate = std::bind(&Tegra::MaxwellDeviceMemoryManager::Allocate, &smmu, _1);
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//: std::bind(&Tegra::MaxwellDeviceMemoryManager::Allocate, &smmu, _1);
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while ((address = allocate(static_cast<size_t>(handle_description->aligned_size))) == 0) {
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handle_description->d_address = address;
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smmu.Map(address, handle_description->address, handle_description->aligned_size,
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session_id);
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session->smmu_id);
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}
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handle_description->pins++;
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@ -25,6 +25,8 @@ class Host1x;
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} // namespace Tegra
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namespace Service::Nvidia::NvCore {
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class Container;
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/**
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* @brief The nvmap core class holds the global state for nvmap and provides methods to manage
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* handles
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@ -109,7 +111,7 @@ public:
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bool can_unlock; //!< If the address region is ready to be unlocked
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};
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explicit NvMap(Tegra::Host1x::Host1x& host1x);
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explicit NvMap(Container& core, Tegra::Host1x::Host1x& host1x);
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/**
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* @brief Creates an unallocated handle of the given size
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* @return If the handle was removed from the map
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*/
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bool TryRemoveHandle(const Handle& handle_description);
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Container& core;
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};
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} // namespace Service::Nvidia::NvCore
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@ -44,7 +44,8 @@ bool AddressSpaceContains(const Common::PageTable& table, const Common::ProcessA
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// from outside classes. This also allows modification to the internals of the memory
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// subsystem without needing to rebuild all files that make use of the memory interface.
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struct Memory::Impl {
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explicit Impl(Core::System& system_) : system{system_} {}
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explicit Impl(Core::System& system_)
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: system{system_} {}
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void SetCurrentPageTable(Kernel::KProcess& process) {
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current_page_table = &process.GetPageTable().GetImpl();
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void HandleRasterizerDownload(VAddr v_address, size_t size) {
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const auto* p = GetPointerImpl(
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v_address, []() {}, []() {});
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auto& gpu_device_memory = system.Host1x().MemoryManager();
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DAddr address =
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gpu_device_memory.GetAddressFromPAddr(system.DeviceMemory().GetRawPhysicalAddr(p));
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if (!gpu_device_memory) [[unlikely]] {
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gpu_device_memory = &system.Host1x().MemoryManager();
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}
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const size_t core = system.GetCurrentHostThreadID();
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auto& current_area = rasterizer_read_areas[core];
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gpu_device_memory->ApplyOpOnPointer(
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p, scratch_buffers[core], [&](DAddr address) {
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const DAddr end_address = address + size;
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if (current_area.start_address <= address && end_address <= current_area.end_address)
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[[likely]] {
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return;
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}
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current_area = system.GPU().OnCPURead(address, size);
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});
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}
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void HandleRasterizerWrite(VAddr v_address, size_t size) {
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const auto* p = GetPointerImpl(
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v_address, []() {}, []() {});
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PAddr address = system.DeviceMemory().GetRawPhysicalAddr(p);
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constexpr size_t sys_core = Core::Hardware::NUM_CPU_CORES - 1;
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const size_t core = std::min(system.GetCurrentHostThreadID(),
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sys_core); // any other calls threads go to syscore.
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if (!gpu_device_memory) [[unlikely]] {
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gpu_device_memory = &system.Host1x().MemoryManager();
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}
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// Guard on sys_core;
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if (core == sys_core) [[unlikely]] {
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sys_core_guard.lock();
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@ -846,6 +852,8 @@ struct Memory::Impl {
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sys_core_guard.unlock();
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}
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});
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gpu_device_memory->ApplyOpOnPointer(
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p, scratch_buffers[core], [&](DAddr address) {
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auto& current_area = rasterizer_write_areas[core];
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PAddr subaddress = address >> YUZU_PAGEBITS;
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bool do_collection = current_area.last_address == subaddress;
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@ -857,6 +865,7 @@ struct Memory::Impl {
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current_area.last_address = subaddress;
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}
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gpu_dirty_managers[core].Collect(address, size);
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});
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}
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struct GPUDirtyState {
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@ -872,10 +881,12 @@ struct Memory::Impl {
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}
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Core::System& system;
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Tegra::MaxwellDeviceMemoryManager* gpu_device_memory{};
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Common::PageTable* current_page_table = nullptr;
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std::array<VideoCore::RasterizerDownloadArea, Core::Hardware::NUM_CPU_CORES>
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rasterizer_read_areas{};
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std::array<GPUDirtyState, Core::Hardware::NUM_CPU_CORES> rasterizer_write_areas{};
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std::array<Common::ScratchBuffer<u32>, Core::Hardware::NUM_CPU_CORES> scratch_buffers{};
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std::span<Core::GPUDirtyMemoryManager> gpu_dirty_managers;
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std::mutex sys_core_guard;
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@ -554,9 +554,8 @@ void RasterizerOpenGL::InvalidateRegion(DAddr addr, u64 size, VideoCommon::Cache
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}
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}
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bool RasterizerOpenGL::OnCPUWrite(PAddr p_addr, u64 size) {
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bool RasterizerOpenGL::OnCPUWrite(DAddr addr, u64 size) {
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MICROPROFILE_SCOPE(OpenGL_CacheManagement);
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const DAddr addr = device_memory.GetAddressFromPAddr(p_addr);
|
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if (addr == 0 || size == 0) {
|
||||
return false;
|
||||
}
|
||||
|
@ -577,9 +576,9 @@ bool RasterizerOpenGL::OnCPUWrite(PAddr p_addr, u64 size) {
|
|||
return false;
|
||||
}
|
||||
|
||||
void RasterizerOpenGL::OnCacheInvalidation(PAddr p_addr, u64 size) {
|
||||
void RasterizerOpenGL::OnCacheInvalidation(DAddr addr, u64 size) {
|
||||
MICROPROFILE_SCOPE(OpenGL_CacheManagement);
|
||||
const DAddr addr = device_memory.GetAddressFromPAddr(p_addr);
|
||||
|
||||
if (addr == 0 || size == 0) {
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -602,8 +602,7 @@ void RasterizerVulkan::InnerInvalidation(std::span<const std::pair<DAddr, std::s
|
|||
}
|
||||
}
|
||||
|
||||
bool RasterizerVulkan::OnCPUWrite(PAddr p_addr, u64 size) {
|
||||
const DAddr addr = device_memory.GetAddressFromPAddr(p_addr);
|
||||
bool RasterizerVulkan::OnCPUWrite(DAddr addr, u64 size) {
|
||||
if (addr == 0 || size == 0) {
|
||||
return false;
|
||||
}
|
||||
|
@ -624,8 +623,7 @@ bool RasterizerVulkan::OnCPUWrite(PAddr p_addr, u64 size) {
|
|||
return false;
|
||||
}
|
||||
|
||||
void RasterizerVulkan::OnCacheInvalidation(PAddr p_addr, u64 size) {
|
||||
const DAddr addr = device_memory.GetAddressFromPAddr(p_addr);
|
||||
void RasterizerVulkan::OnCacheInvalidation(DAddr addr, u64 size) {
|
||||
if (addr == 0 || size == 0) {
|
||||
return;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue