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glsl: SSBO access fixes and wip SampleExplicitLod implementation.

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This commit is contained in:
ameerj 2021-05-28 13:55:07 -04:00
parent f6bbc76336
commit 453cd25da5
2 changed files with 19 additions and 4 deletions
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15
src/shader_recompiler/backend/glsl/emit_glsl_image.cpp
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@ -46,7 +46,20 @@ void EmitImageSampleExplicitLod([[maybe_unused]] EmitContext& ctx, [[maybe_unuse
[[maybe_unused]] std::string_view coords,
[[maybe_unused]] std::string_view lod_lc,
[[maybe_unused]] const IR::Value& offset) {
throw NotImplementedException("GLSL Instruction");
const auto info{inst.Flags<IR::TextureInstInfo>()};
if (info.has_bias) {
throw NotImplementedException("Bias texture samples");
}
if (info.has_lod_clamp) {
throw NotImplementedException("Lod clamp samples");
}
const auto texture{Texture(ctx, info, index)};
if (!offset.IsEmpty()) {
ctx.AddF32x4("{}=textureLodOffset({},{},{},ivec2({}));", inst, texture, coords, lod_lc,
ctx.reg_alloc.Consume(offset));
} else {
ctx.AddF32x4("{}=textureLod({},{},{});", inst, texture, coords, lod_lc);
}
}
void EmitImageSampleDrefImplicitLod([[maybe_unused]] EmitContext& ctx,

8
src/shader_recompiler/backend/glsl/emit_glsl_memory.cpp
View file

@ -81,13 +81,15 @@ void EmitWriteStorageS16([[maybe_unused]] EmitContext& ctx,
void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
std::string_view value) {
ctx.Add("ssbo{}[{}]={};", binding.U32(), offset.U32(), value);
const auto offset_var{ctx.reg_alloc.Consume(offset)};
ctx.Add("ssbo{}[{}]={};", binding.U32(), offset_var, value);
}
void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
std::string_view value) {
ctx.Add("ssbo{}[{}]={}.x;", binding.U32(), offset.U32(), value);
ctx.Add("ssbo{}[{}]={}.y;", binding.U32(), offset.U32() + 1, value);
const auto offset_var{ctx.reg_alloc.Consume(offset)};
ctx.Add("ssbo{}[{}]={}.x;", binding.U32(), offset_var, value);
ctx.Add("ssbo{}[{}+1]={}.y;", binding.U32(), offset_var, value);
}
void EmitWriteStorage128([[maybe_unused]] EmitContext& ctx,