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Merge pull request #384 from Subv/nvhost-remap
Nvdrv/nvhost-as-gpu: Implemented the ioctl REMAP command.
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commit
bf25299272
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@ -27,6 +27,11 @@ u32 nvhost_as_gpu::ioctl(Ioctl command, const std::vector<u8>& input, std::vecto
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case IoctlCommand::IocGetVaRegionsCommand:
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return GetVARegions(input, output);
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}
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if (static_cast<IoctlCommand>(command.cmd.Value()) == IoctlCommand::IocRemapCommand)
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return Remap(input, output);
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UNIMPLEMENTED_MSG("Unimplemented ioctl command");
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return 0;
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}
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@ -56,6 +61,36 @@ u32 nvhost_as_gpu::AllocateSpace(const std::vector<u8>& input, std::vector<u8>&
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return 0;
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}
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u32 nvhost_as_gpu::Remap(const std::vector<u8>& input, std::vector<u8>& output) {
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size_t num_entries = input.size() / sizeof(IoctlRemapEntry);
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NGLOG_WARNING(Service_NVDRV, "(STUBBED) called, num_entries=0x{:X}", num_entries);
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std::vector<IoctlRemapEntry> entries(num_entries);
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std::memcpy(entries.data(), input.data(), input.size());
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auto& gpu = Core::System::GetInstance().GPU();
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for (const auto& entry : entries) {
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NGLOG_WARNING(Service_NVDRV, "remap entry, offset=0x{:X} handle=0x{:X} pages=0x{:X}",
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entry.offset, entry.nvmap_handle, entry.pages);
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Tegra::GPUVAddr offset = static_cast<Tegra::GPUVAddr>(entry.offset) << 0x10;
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auto object = nvmap_dev->GetObject(entry.nvmap_handle);
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ASSERT(object);
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ASSERT(object->status == nvmap::Object::Status::Allocated);
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u64 size = static_cast<u64>(entry.pages) << 0x10;
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ASSERT(size <= object->size);
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Tegra::GPUVAddr returned = gpu.memory_manager->MapBufferEx(object->addr, offset, size);
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ASSERT(returned == offset);
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}
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std::memcpy(output.data(), entries.data(), output.size());
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return 0;
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}
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u32 nvhost_as_gpu::MapBufferEx(const std::vector<u8>& input, std::vector<u8>& output) {
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IoctlMapBufferEx params{};
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std::memcpy(¶ms, input.data(), input.size());
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@ -73,6 +108,16 @@ u32 nvhost_as_gpu::MapBufferEx(const std::vector<u8>& input, std::vector<u8>& ou
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auto object = nvmap_dev->GetObject(params.nvmap_handle);
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ASSERT(object);
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// We can only map objects that have already been assigned a CPU address.
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ASSERT(object->status == nvmap::Object::Status::Allocated);
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ASSERT(params.buffer_offset == 0);
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// The real nvservices doesn't make a distinction between handles and ids, and
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// object can only have one handle and it will be the same as its id. Assert that this is the
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// case to prevent unexpected behavior.
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ASSERT(object->id == params.nvmap_handle);
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auto& gpu = Core::System::GetInstance().GPU();
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if (params.flags & 1) {
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@ -26,6 +26,7 @@ private:
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enum class IoctlCommand : u32_le {
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IocInitalizeExCommand = 0x40284109,
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IocAllocateSpaceCommand = 0xC0184102,
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IocRemapCommand = 0x00000014,
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IocMapBufferExCommand = 0xC0284106,
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IocBindChannelCommand = 0x40044101,
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IocGetVaRegionsCommand = 0xC0404108,
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@ -54,6 +55,16 @@ private:
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};
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static_assert(sizeof(IoctlAllocSpace) == 24, "IoctlInitalizeEx is incorrect size");
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struct IoctlRemapEntry {
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u16_le flags;
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u16_le kind;
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u32_le nvmap_handle;
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INSERT_PADDING_WORDS(1);
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u32_le offset;
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u32_le pages;
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};
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static_assert(sizeof(IoctlRemapEntry) == 20, "IoctlRemapEntry is incorrect size");
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struct IoctlMapBufferEx {
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u32_le flags; // bit0: fixed_offset, bit2: cacheable
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u32_le kind; // -1 is default
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@ -91,6 +102,7 @@ private:
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u32 InitalizeEx(const std::vector<u8>& input, std::vector<u8>& output);
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u32 AllocateSpace(const std::vector<u8>& input, std::vector<u8>& output);
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u32 Remap(const std::vector<u8>& input, std::vector<u8>& output);
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u32 MapBufferEx(const std::vector<u8>& input, std::vector<u8>& output);
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u32 BindChannel(const std::vector<u8>& input, std::vector<u8>& output);
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u32 GetVARegions(const std::vector<u8>& input, std::vector<u8>& output);
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