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video_core: Refactor command_processor.
Inline the WriteReg helper as it is called ~20k times per frame.
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@ -28,7 +28,12 @@ enum class BufferMethods {
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CountBufferMethods = 0x40,
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CountBufferMethods = 0x40,
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};
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};
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void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params) {
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MICROPROFILE_DEFINE(ProcessCommandLists, "GPU", "Execute command buffer", MP_RGB(128, 128, 192));
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void GPU::ProcessCommandLists(const std::vector<CommandListHeader>& commands) {
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MICROPROFILE_SCOPE(ProcessCommandLists);
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auto WriteReg = [this](u32 method, u32 subchannel, u32 value, u32 remaining_params) {
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LOG_TRACE(HW_GPU,
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LOG_TRACE(HW_GPU,
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"Processing method {:08X} on subchannel {} value "
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"Processing method {:08X} on subchannel {} value "
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"{:08X} remaining params {}",
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"{:08X} remaining params {}",
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@ -67,12 +72,8 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
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default:
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default:
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UNIMPLEMENTED_MSG("Unimplemented engine");
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UNIMPLEMENTED_MSG("Unimplemented engine");
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}
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}
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}
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};
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MICROPROFILE_DEFINE(ProcessCommandLists, "GPU", "Execute command buffer", MP_RGB(128, 128, 192));
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void GPU::ProcessCommandLists(const std::vector<CommandListHeader>& commands) {
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MICROPROFILE_SCOPE(ProcessCommandLists);
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for (auto entry : commands) {
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for (auto entry : commands) {
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Tegra::GPUVAddr address = entry.Address();
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Tegra::GPUVAddr address = entry.Address();
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u32 size = entry.sz;
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u32 size = entry.sz;
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@ -132,9 +132,6 @@ public:
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const Tegra::MemoryManager& MemoryManager() const;
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const Tegra::MemoryManager& MemoryManager() const;
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private:
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private:
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/// Writes a single register in the engine bound to the specified subchannel
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void WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params);
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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/// Mapping of command subchannels to their bound engine ids.
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/// Mapping of command subchannels to their bound engine ids.
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