Ryujinx/ARMeilleure/Translation
Wunk 17620d18db
ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147)
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection

Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.

* ARMeilleure: Add initial support for EVEX instruction encoding

Does not implement rounding, or exception controls.

* ARMeilleure: Add `X86Vpternlogd`

Accelerates the vector-`Not` instruction.

* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}

* ARMeilleure: Add check for `XCR0` flags

Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.

* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting

* ARMeilleure: Move XCR0 procedure to GetXcr0Eax

* ARMeilleure: Add `XCR0` to `FeatureInfo` structure

* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly

Avoids an additional allocation

* ARMeilleure: Formatting fixes

* ARMeilleure: Fix EVEX encoding src2 register index

> Just like in VEX prefix, vvvv is provided in inverted form.

* ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I`

Passes unit tests, verified instruction utilization

* ARMeilleure: Fix EVEX register operand designations

Operand 2 was being sourced improperly.

EVEX encoded instructions source their operands like so:
Operand 1: ModRM:reg
Operand 2: EVEX.vvvvv
Operand 3: ModRM:r/m
Operand 4: Imm

This fixes the improper register designations when emitting vpternlog.
Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions.

* ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V`

* ARMeilleure: PTC version bump

* ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail

* ARMeilleure: Update EVEX encoding comment capitalization
2023-03-20 16:09:24 -03:00
..
Cache Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
PTC ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147) 2023-03-20 16:09:24 -03:00
ArmEmitterContext.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
Compiler.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00
CompilerContext.cs
CompilerOptions.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00
ControlFlowGraph.cs
DelegateHelper.cs
DelegateInfo.cs
Delegates.cs
DispatcherFunction.cs
Dominance.cs
EmitterContext.cs
GuestFunction.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
IntervalTree.cs
RegisterToLocal.cs
RegisterUsage.cs
RejitRequest.cs
SsaConstruction.cs
SsaDeconstruction.cs
TranslatedFunction.cs Remove use of GetFunctionPointerForDelegate to get JIT cache function pointer (#4337) 2023-01-23 22:37:53 +00:00
Translator.cs Remove use of GetFunctionPointerForDelegate to get JIT cache function pointer (#4337) 2023-01-23 22:37:53 +00:00
TranslatorCache.cs
TranslatorQueue.cs
TranslatorStubs.cs Implement JIT Arm64 backend (#4114) 2023-01-10 19:16:59 -03:00