mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-08 18:08:33 +00:00
17620d18db
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection
Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as
short-hands for `F+VL` and `F+VL+DQ`.
* ARMeilleure: Add initial support for EVEX instruction encoding
Does not implement rounding, or exception controls.
* ARMeilleure: Add `X86Vpternlogd`
Accelerates the vector-`Not` instruction.
* ARMeilleure: Add check for `OSXSAVE` for AVX{2,512}
* ARMeilleure: Add check for `XCR0` flags
Add XCR0 register checks for AVX and AVX512F, following the guidelines
from section 14.3 and 15.2 from the Intel Architecture Software
Developer's Manual.
* ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting
* ARMeilleure: Move XCR0 procedure to GetXcr0Eax
* ARMeilleure: Add `XCR0` to `FeatureInfo` structure
* ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly
Avoids an additional allocation
* ARMeilleure: Formatting fixes
* ARMeilleure: Fix EVEX encoding src2 register index
> Just like in VEX prefix, vvvv is provided in inverted form.
* ARMeilleure: Add `X86Vpternlogd` acceleration to `Vmvn_I`
Passes unit tests, verified instruction utilization
* ARMeilleure: Fix EVEX register operand designations
Operand 2 was being sourced improperly.
EVEX encoded instructions source their operands like so:
Operand 1: ModRM:reg
Operand 2: EVEX.vvvvv
Operand 3: ModRM:r/m
Operand 4: Imm
This fixes the improper register designations when emitting vpternlog.
Now "dest", "src1", "src2" arguments emit in the proper order in EVEX instructions.
* ARMeilleure: Add `X86Vpternlogd` acceleration to `Orn_V`
* ARMeilleure: PTC version bump
* ARMeilleure: Update EVEX encoding Debug.Assert to Debug.Fail
* ARMeilleure: Update EVEX encoding comment capitalization
229 lines
3.6 KiB
C#
229 lines
3.6 KiB
C#
namespace ARMeilleure.CodeGen.X86
|
|
{
|
|
enum X86Instruction
|
|
{
|
|
None,
|
|
Add,
|
|
Addpd,
|
|
Addps,
|
|
Addsd,
|
|
Addss,
|
|
Aesdec,
|
|
Aesdeclast,
|
|
Aesenc,
|
|
Aesenclast,
|
|
Aesimc,
|
|
And,
|
|
Andnpd,
|
|
Andnps,
|
|
Andpd,
|
|
Andps,
|
|
Blendvpd,
|
|
Blendvps,
|
|
Bsr,
|
|
Bswap,
|
|
Call,
|
|
Cmovcc,
|
|
Cmp,
|
|
Cmppd,
|
|
Cmpps,
|
|
Cmpsd,
|
|
Cmpss,
|
|
Cmpxchg,
|
|
Cmpxchg16b,
|
|
Cmpxchg8,
|
|
Comisd,
|
|
Comiss,
|
|
Crc32,
|
|
Crc32_16,
|
|
Crc32_8,
|
|
Cvtdq2pd,
|
|
Cvtdq2ps,
|
|
Cvtpd2dq,
|
|
Cvtpd2ps,
|
|
Cvtps2dq,
|
|
Cvtps2pd,
|
|
Cvtsd2si,
|
|
Cvtsd2ss,
|
|
Cvtsi2sd,
|
|
Cvtsi2ss,
|
|
Cvtss2sd,
|
|
Cvtss2si,
|
|
Div,
|
|
Divpd,
|
|
Divps,
|
|
Divsd,
|
|
Divss,
|
|
Gf2p8affineqb,
|
|
Haddpd,
|
|
Haddps,
|
|
Idiv,
|
|
Imul,
|
|
Imul128,
|
|
Insertps,
|
|
Jmp,
|
|
Ldmxcsr,
|
|
Lea,
|
|
Maxpd,
|
|
Maxps,
|
|
Maxsd,
|
|
Maxss,
|
|
Minpd,
|
|
Minps,
|
|
Minsd,
|
|
Minss,
|
|
Mov,
|
|
Mov16,
|
|
Mov8,
|
|
Movd,
|
|
Movdqu,
|
|
Movhlps,
|
|
Movlhps,
|
|
Movq,
|
|
Movsd,
|
|
Movss,
|
|
Movsx16,
|
|
Movsx32,
|
|
Movsx8,
|
|
Movzx16,
|
|
Movzx8,
|
|
Mul128,
|
|
Mulpd,
|
|
Mulps,
|
|
Mulsd,
|
|
Mulss,
|
|
Neg,
|
|
Not,
|
|
Or,
|
|
Paddb,
|
|
Paddd,
|
|
Paddq,
|
|
Paddw,
|
|
Palignr,
|
|
Pand,
|
|
Pandn,
|
|
Pavgb,
|
|
Pavgw,
|
|
Pblendvb,
|
|
Pclmulqdq,
|
|
Pcmpeqb,
|
|
Pcmpeqd,
|
|
Pcmpeqq,
|
|
Pcmpeqw,
|
|
Pcmpgtb,
|
|
Pcmpgtd,
|
|
Pcmpgtq,
|
|
Pcmpgtw,
|
|
Pextrb,
|
|
Pextrd,
|
|
Pextrq,
|
|
Pextrw,
|
|
Pinsrb,
|
|
Pinsrd,
|
|
Pinsrq,
|
|
Pinsrw,
|
|
Pmaxsb,
|
|
Pmaxsd,
|
|
Pmaxsw,
|
|
Pmaxub,
|
|
Pmaxud,
|
|
Pmaxuw,
|
|
Pminsb,
|
|
Pminsd,
|
|
Pminsw,
|
|
Pminub,
|
|
Pminud,
|
|
Pminuw,
|
|
Pmovsxbw,
|
|
Pmovsxdq,
|
|
Pmovsxwd,
|
|
Pmovzxbw,
|
|
Pmovzxdq,
|
|
Pmovzxwd,
|
|
Pmulld,
|
|
Pmullw,
|
|
Pop,
|
|
Popcnt,
|
|
Por,
|
|
Pshufb,
|
|
Pshufd,
|
|
Pslld,
|
|
Pslldq,
|
|
Psllq,
|
|
Psllw,
|
|
Psrad,
|
|
Psraw,
|
|
Psrld,
|
|
Psrlq,
|
|
Psrldq,
|
|
Psrlw,
|
|
Psubb,
|
|
Psubd,
|
|
Psubq,
|
|
Psubw,
|
|
Punpckhbw,
|
|
Punpckhdq,
|
|
Punpckhqdq,
|
|
Punpckhwd,
|
|
Punpcklbw,
|
|
Punpckldq,
|
|
Punpcklqdq,
|
|
Punpcklwd,
|
|
Push,
|
|
Pxor,
|
|
Rcpps,
|
|
Rcpss,
|
|
Ror,
|
|
Roundpd,
|
|
Roundps,
|
|
Roundsd,
|
|
Roundss,
|
|
Rsqrtps,
|
|
Rsqrtss,
|
|
Sar,
|
|
Setcc,
|
|
Sha256Msg1,
|
|
Sha256Msg2,
|
|
Sha256Rnds2,
|
|
Shl,
|
|
Shr,
|
|
Shufpd,
|
|
Shufps,
|
|
Sqrtpd,
|
|
Sqrtps,
|
|
Sqrtsd,
|
|
Sqrtss,
|
|
Stmxcsr,
|
|
Sub,
|
|
Subpd,
|
|
Subps,
|
|
Subsd,
|
|
Subss,
|
|
Test,
|
|
Unpckhpd,
|
|
Unpckhps,
|
|
Unpcklpd,
|
|
Unpcklps,
|
|
Vblendvpd,
|
|
Vblendvps,
|
|
Vcvtph2ps,
|
|
Vcvtps2ph,
|
|
Vfmadd231ps,
|
|
Vfmadd231sd,
|
|
Vfmadd231ss,
|
|
Vfmsub231sd,
|
|
Vfmsub231ss,
|
|
Vfnmadd231ps,
|
|
Vfnmadd231sd,
|
|
Vfnmadd231ss,
|
|
Vfnmsub231sd,
|
|
Vfnmsub231ss,
|
|
Vpblendvb,
|
|
Vpternlogd,
|
|
Xor,
|
|
Xorpd,
|
|
Xorps,
|
|
|
|
Count
|
|
}
|
|
} |