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Ryujinx/ChocolArm64/Instruction
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LDj3SNuD c228cf320d Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdLogical.cs

* Update AVectorHelper.cs

* Update ASoftFallback.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Improve CountSetBits8() algorithm.

* Improve CountSetBits8() algorithm.
2018-07-03 03:31:16 -03:00
..
AInst.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
AInstEmitAlu.cs Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code 2018-06-02 11:44:52 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs Implement SvcGetThreadContext3 2018-06-26 01:10:15 -03:00
AInstEmitFlow.cs Stub a few services, add support for generating call stacks on the CPU 2018-04-22 01:22:46 -03:00
AInstEmitHash.cs Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) 2018-06-25 22:32:29 -03:00
AInstEmitMemory.cs Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code 2018-06-02 11:44:52 -03:00
AInstEmitMemoryEx.cs Fix some thread sync issues (#172) 2018-06-21 23:05:42 -03:00
AInstEmitMemoryHelper.cs Improved logging (#103) 2018-04-24 15:57:39 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212) 2018-07-03 03:31:16 -03:00
AInstEmitSimdCmp.cs Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) 2018-06-25 22:32:29 -03:00
AInstEmitSimdCvt.cs Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushader 2018-05-18 14:44:49 -03:00
AInstEmitSimdHelper.cs Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204) 2018-06-30 12:40:41 -03:00
AInstEmitSimdLogical.cs Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212) 2018-07-03 03:31:16 -03:00
AInstEmitSimdMemory.cs
AInstEmitSimdMove.cs Add intrinsics support (#121) 2018-05-11 20:10:27 -03:00
AInstEmitSimdShift.cs CPU fix for the cases using a Mask with shift = 0 2018-03-14 01:59:22 -03:00
AInstEmitSystem.cs Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count 2018-03-13 21:24:32 -03:00
AInstEmitter.cs
AInstInterpreter.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
ASoftFallback.cs Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212) 2018-07-03 03:31:16 -03:00
ASoftFloat.cs Implement Frsqrte_S (#72) 2018-04-05 20:36:19 -03:00
AVectorHelper.cs Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212) 2018-07-03 03:31:16 -03:00