yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-25 08:05:38 +00:00
Code Issues Packages Projects Releases Wiki Activity
unicorn/qemu/target/riscv/insn32.decode

60 lines
2.5 KiB
Plaintext
Raw Normal View History

target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
#
# RISC-V translation routines for the RVXI Base Integer Instruction Set.
#
# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2 or later, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
%rs2 20:5
%rs1 15:5
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
%rd 7:5
# immediates:
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
%imm_i 20:s12
target/riscv: Convert RV32I load/store insns to decodetree Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu
2019-03-18 19:59:40 +00:00
%imm_s 25:s7 7:5
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
%imm_u 12:s20 !function=ex_shift_12
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
# Argument sets:
&b imm rs2 rs1
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
# Formats 32:
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
target/riscv: Convert RV32I load/store insns to decodetree Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu
2019-03-18 19:59:40 +00:00
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
@u .................... ..... ....... imm=%imm_u %rd
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
@j .................... ..... ....... imm=%imm_j %rd
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
auipc .................... ..... 0010111 @u
jal .................... ..... 1101111 @j
jalr ............ ..... 000 ..... 1100111 @i
beq ....... ..... ..... 000 ..... 1100011 @b
bne ....... ..... ..... 001 ..... 1100011 @b
blt ....... ..... ..... 100 ..... 1100011 @b
bge ....... ..... ..... 101 ..... 1100011 @b
bltu ....... ..... ..... 110 ..... 1100011 @b
bgeu ....... ..... ..... 111 ..... 1100011 @b
target/riscv: Convert RV32I load/store insns to decodetree Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu
2019-03-18 19:59:40 +00:00
lb ............ ..... 000 ..... 0000011 @i
lh ............ ..... 001 ..... 0000011 @i
lw ............ ..... 010 ..... 0000011 @i
lbu ............ ..... 100 ..... 0000011 @i
lhu ............ ..... 101 ..... 0000011 @i
sb ....... ..... ..... 000 ..... 0100011 @s
sh ....... ..... ..... 001 ..... 0100011 @s
sw ....... ..... ..... 010 ..... 0100011 @s
Reference in a new issue Copy permalink