Bastian Koppelmann 1024ceb4df target/riscv: Convert RV64I load/store insns to decodetree ... this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu		2019-03-18 16:02:16 -04:00
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insn_trans	target/riscv: Convert RV64I load/store insns to decodetree	2019-03-18 16:02:16 -04:00
cpu.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
cpu.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
cpu_bits.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
cpu_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
cpu_user.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
csr.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
fpu_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
helper.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
insn32.decode	target/riscv: Convert RV32I load/store insns to decodetree	2019-03-18 15:59:43 -04:00
instmap.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
Makefile.objs	target/riscv: Convert RV64I load/store insns to decodetree	2019-03-18 16:02:16 -04:00
op_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
pmp.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
pmp.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
translate.c	target/riscv: Convert RV64I load/store insns to decodetree	2019-03-18 16:02:16 -04:00
unicorn.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00