mirror of
https://github.com/yuzu-emu/unicorn.git
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1310 lines
43 KiB
C
1310 lines
43 KiB
C
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/*
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* Generic vector operation expansion
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*
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* Copyright (c) 2018 Linaro
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "tcg.h"
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#include "tcg-op.h"
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#include "tcg-op-gvec.h"
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#include "tcg-gvec-desc.h"
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#define MAX_UNROLL 4
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/* Verify vector size and alignment rules. OFS should be the OR of all
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of the operand offsets so that we can check them all at once. */
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static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
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{
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uint32_t opr_align = oprsz >= 16 ? 15 : 7;
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uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
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tcg_debug_assert(oprsz > 0);
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tcg_debug_assert(oprsz <= maxsz);
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tcg_debug_assert((oprsz & opr_align) == 0);
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tcg_debug_assert((maxsz & max_align) == 0);
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tcg_debug_assert((ofs & max_align) == 0);
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}
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/* Verify vector overlap rules for two operands. */
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static void check_overlap_2(uint32_t d, uint32_t a, uint32_t s)
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{
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tcg_debug_assert(d == a || d + s <= a || a + s <= d);
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}
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/* Verify vector overlap rules for three operands. */
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static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s)
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{
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check_overlap_2(d, a, s);
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check_overlap_2(d, b, s);
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check_overlap_2(a, b, s);
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}
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/* Verify vector overlap rules for four operands. */
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static void check_overlap_4(uint32_t d, uint32_t a, uint32_t b,
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uint32_t c, uint32_t s)
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{
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check_overlap_2(d, a, s);
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check_overlap_2(d, b, s);
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check_overlap_2(d, c, s);
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check_overlap_2(a, b, s);
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check_overlap_2(a, c, s);
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check_overlap_2(b, c, s);
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}
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/* Create a descriptor from components. */
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uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
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{
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uint32_t desc = 0;
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assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
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assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
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assert(data == sextract32(data, 0, SIMD_DATA_BITS));
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oprsz = (oprsz / 8) - 1;
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maxsz = (maxsz / 8) - 1;
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desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
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desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
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desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
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return desc;
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}
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/* Generate a call to a gvec-style helper with two vector operands. */
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void tcg_gen_gvec_2_ool(TCGContext *s, uint32_t dofs, uint32_t aofs,
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uint32_t oprsz, uint32_t maxsz, int32_t data,
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gen_helper_gvec_2 *fn)
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{
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TCGv_ptr a0, a1;
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TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
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a0 = tcg_temp_new_ptr(s);
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a1 = tcg_temp_new_ptr(s);
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tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
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tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
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fn(s, a0, a1, desc);
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tcg_temp_free_ptr(s, a0);
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tcg_temp_free_ptr(s, a1);
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tcg_temp_free_i32(s, desc);
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}
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/* Generate a call to a gvec-style helper with three vector operands. */
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void tcg_gen_gvec_3_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t oprsz, uint32_t maxsz, int32_t data,
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gen_helper_gvec_3 *fn)
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{
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TCGv_ptr a0, a1, a2;
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TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
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a0 = tcg_temp_new_ptr(s);
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a1 = tcg_temp_new_ptr(s);
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a2 = tcg_temp_new_ptr(s);
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tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
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tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
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tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
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fn(s, a0, a1, a2, desc);
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tcg_temp_free_ptr(s, a0);
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tcg_temp_free_ptr(s, a1);
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tcg_temp_free_ptr(s, a2);
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tcg_temp_free_i32(s, desc);
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}
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/* Generate a call to a gvec-style helper with four vector operands. */
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void tcg_gen_gvec_4_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
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int32_t data, gen_helper_gvec_4 *fn)
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{
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TCGv_ptr a0, a1, a2, a3;
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TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
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a0 = tcg_temp_new_ptr(s);
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a1 = tcg_temp_new_ptr(s);
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a2 = tcg_temp_new_ptr(s);
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a3 = tcg_temp_new_ptr(s);
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tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
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tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
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tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
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tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
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fn(s, a0, a1, a2, a3, desc);
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tcg_temp_free_ptr(s, a0);
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tcg_temp_free_ptr(s, a1);
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tcg_temp_free_ptr(s, a2);
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tcg_temp_free_ptr(s, a3);
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tcg_temp_free_i32(s, desc);
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}
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/* Generate a call to a gvec-style helper with five vector operands. */
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void tcg_gen_gvec_5_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t cofs, uint32_t xofs, uint32_t oprsz,
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uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn)
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{
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TCGv_ptr a0, a1, a2, a3, a4;
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TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
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a0 = tcg_temp_new_ptr(s);
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a1 = tcg_temp_new_ptr(s);
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a2 = tcg_temp_new_ptr(s);
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a3 = tcg_temp_new_ptr(s);
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a4 = tcg_temp_new_ptr(s);
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tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
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tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
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tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
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tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
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tcg_gen_addi_ptr(s, a4, s->cpu_env, xofs);
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fn(s, a0, a1, a2, a3, a4, desc);
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tcg_temp_free_ptr(s, a0);
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tcg_temp_free_ptr(s, a1);
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tcg_temp_free_ptr(s, a2);
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tcg_temp_free_ptr(s, a3);
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tcg_temp_free_ptr(s, a4);
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tcg_temp_free_i32(s, desc);
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}
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/* Generate a call to a gvec-style helper with three vector operands
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and an extra pointer operand. */
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void tcg_gen_gvec_2_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs,
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TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
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int32_t data, gen_helper_gvec_2_ptr *fn)
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{
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TCGv_ptr a0, a1;
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TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
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a0 = tcg_temp_new_ptr(s);
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a1 = tcg_temp_new_ptr(s);
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tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
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tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
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fn(s, a0, a1, ptr, desc);
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tcg_temp_free_ptr(s, a0);
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tcg_temp_free_ptr(s, a1);
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tcg_temp_free_i32(s, desc);
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}
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/* Generate a call to a gvec-style helper with three vector operands
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and an extra pointer operand. */
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void tcg_gen_gvec_3_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
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TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
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int32_t data, gen_helper_gvec_3_ptr *fn)
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{
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TCGv_ptr a0, a1, a2;
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TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
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a0 = tcg_temp_new_ptr(s);
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a1 = tcg_temp_new_ptr(s);
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a2 = tcg_temp_new_ptr(s);
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tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
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tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
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tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
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fn(s, a0, a1, a2, ptr, desc);
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tcg_temp_free_ptr(s, a0);
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tcg_temp_free_ptr(s, a1);
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tcg_temp_free_ptr(s, a2);
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tcg_temp_free_i32(s, desc);
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}
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/* Generate a call to a gvec-style helper with four vector operands
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and an extra pointer operand. */
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void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
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uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
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uint32_t maxsz, int32_t data,
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gen_helper_gvec_4_ptr *fn)
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{
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TCGv_ptr a0, a1, a2, a3;
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TCGv_i32 desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, data));
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a0 = tcg_temp_new_ptr(s);
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a1 = tcg_temp_new_ptr(s);
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a2 = tcg_temp_new_ptr(s);
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a3 = tcg_temp_new_ptr(s);
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tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
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tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
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tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
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tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
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fn(s, a0, a1, a2, a3, ptr, desc);
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tcg_temp_free_ptr(s, a0);
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tcg_temp_free_ptr(s, a1);
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tcg_temp_free_ptr(s, a2);
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tcg_temp_free_ptr(s, a3);
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tcg_temp_free_i32(s, desc);
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}
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/* Return true if we want to implement something of OPRSZ bytes
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in units of LNSZ. This limits the expansion of inline code. */
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static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
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{
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uint32_t lnct = oprsz / lnsz;
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return lnct >= 1 && lnct <= MAX_UNROLL;
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}
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static void expand_clr(TCGContext *s, uint32_t dofs, uint32_t maxsz);
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/* Duplicate C as per VECE. */
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uint64_t (dup_const_impl)(unsigned vece, uint64_t c)
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{
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switch (vece) {
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case MO_8:
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return 0x0101010101010101ull * (uint8_t)c;
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case MO_16:
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return 0x0001000100010001ull * (uint16_t)c;
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case MO_32:
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return 0x0000000100000001ull * (uint32_t)c;
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case MO_64:
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return c;
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default:
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g_assert_not_reached();
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}
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}
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/* Duplicate IN into OUT as per VECE. */
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static void gen_dup_i32(TCGContext *s, unsigned vece, TCGv_i32 out, TCGv_i32 in)
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{
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switch (vece) {
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case MO_8:
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tcg_gen_ext8u_i32(s, out, in);
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tcg_gen_muli_i32(s, out, out, 0x01010101);
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break;
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case MO_16:
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tcg_gen_deposit_i32(s, out, in, in, 16, 16);
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break;
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case MO_32:
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tcg_gen_mov_i32(s, out, in);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void gen_dup_i64(TCGContext *s, unsigned vece, TCGv_i64 out, TCGv_i64 in)
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{
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switch (vece) {
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case MO_8:
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tcg_gen_ext8u_i64(s, out, in);
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tcg_gen_muli_i64(s, out, out, 0x0101010101010101ull);
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break;
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case MO_16:
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tcg_gen_ext16u_i64(s, out, in);
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tcg_gen_muli_i64(s, out, out, 0x0001000100010001ull);
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break;
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case MO_32:
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tcg_gen_deposit_i64(s, out, in, in, 32, 32);
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break;
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case MO_64:
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tcg_gen_mov_i64(s, out, in);
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break;
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default:
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g_assert_not_reached();
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}
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}
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/* Set OPRSZ bytes at DOFS to replications of IN_32, IN_64 or IN_C.
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* Only one of IN_32 or IN_64 may be set;
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* IN_C is used if IN_32 and IN_64 are unset.
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*/
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static void do_dup(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
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uint32_t maxsz, TCGv_i32 in_32, TCGv_i64 in_64,
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uint64_t in_c)
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{
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TCGType type;
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TCGv_i64 t_64;
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TCGv_i32 t_32, t_desc;
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TCGv_ptr t_ptr;
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uint32_t i;
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assert(vece <= (in_32 ? MO_32 : MO_64));
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assert(in_32 == NULL || in_64 == NULL);
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/* If we're storing 0, expand oprsz to maxsz. */
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if (in_32 == NULL && in_64 == NULL) {
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in_c = dup_const(vece, in_c);
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if (in_c == 0) {
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oprsz = maxsz;
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}
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}
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type = 0;
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if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
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type = TCG_TYPE_V256;
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||
|
} else if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
|
||
|
type = TCG_TYPE_V128;
|
||
|
} else if (TCG_TARGET_HAS_v64 && check_size_impl(oprsz, 8)
|
||
|
/* Prefer integer when 64-bit host and no variable dup. */
|
||
|
&& !(TCG_TARGET_REG_BITS == 64 && in_32 == NULL
|
||
|
&& (in_64 == NULL || vece == MO_64))) {
|
||
|
type = TCG_TYPE_V64;
|
||
|
}
|
||
|
|
||
|
/* Implement inline with a vector type, if possible. */
|
||
|
if (type != 0) {
|
||
|
TCGv_vec t_vec = tcg_temp_new_vec(s, type);
|
||
|
|
||
|
if (in_32) {
|
||
|
tcg_gen_dup_i32_vec(s, vece, t_vec, in_32);
|
||
|
} else if (in_64) {
|
||
|
tcg_gen_dup_i64_vec(s, vece, t_vec, in_64);
|
||
|
} else {
|
||
|
switch (vece) {
|
||
|
case MO_8:
|
||
|
tcg_gen_dup8i_vec(s, t_vec, in_c);
|
||
|
break;
|
||
|
case MO_16:
|
||
|
tcg_gen_dup16i_vec(s, t_vec, in_c);
|
||
|
break;
|
||
|
case MO_32:
|
||
|
tcg_gen_dup32i_vec(s, t_vec, in_c);
|
||
|
break;
|
||
|
default:
|
||
|
tcg_gen_dup64i_vec(s, t_vec, in_c);
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
i = 0;
|
||
|
if (TCG_TARGET_HAS_v256) {
|
||
|
for (; i + 32 <= oprsz; i += 32) {
|
||
|
tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V256);
|
||
|
}
|
||
|
}
|
||
|
if (TCG_TARGET_HAS_v128) {
|
||
|
for (; i + 16 <= oprsz; i += 16) {
|
||
|
tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V128);
|
||
|
}
|
||
|
}
|
||
|
if (TCG_TARGET_HAS_v64) {
|
||
|
for (; i < oprsz; i += 8) {
|
||
|
tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V64);
|
||
|
}
|
||
|
}
|
||
|
tcg_temp_free_vec(s, t_vec);
|
||
|
goto done;
|
||
|
}
|
||
|
|
||
|
/* Otherwise, inline with an integer type, unless "large". */
|
||
|
if (check_size_impl(oprsz, TCG_TARGET_REG_BITS / 8)) {
|
||
|
t_64 = NULL;
|
||
|
t_32 = NULL;
|
||
|
|
||
|
if (in_32) {
|
||
|
/* We are given a 32-bit variable input. For a 64-bit host,
|
||
|
use a 64-bit operation unless the 32-bit operation would
|
||
|
be simple enough. */
|
||
|
if (TCG_TARGET_REG_BITS == 64
|
||
|
&& (vece != MO_32 || !check_size_impl(oprsz, 4))) {
|
||
|
t_64 = tcg_temp_new_i64(s);
|
||
|
tcg_gen_extu_i32_i64(s, t_64, in_32);
|
||
|
gen_dup_i64(s, vece, t_64, t_64);
|
||
|
} else {
|
||
|
t_32 = tcg_temp_new_i32(s);
|
||
|
gen_dup_i32(s, vece, t_32, in_32);
|
||
|
}
|
||
|
} else if (in_64) {
|
||
|
/* We are given a 64-bit variable input. */
|
||
|
t_64 = tcg_temp_new_i64(s);
|
||
|
gen_dup_i64(s, vece, t_64, in_64);
|
||
|
} else {
|
||
|
/* We are given a constant input. */
|
||
|
/* For 64-bit hosts, use 64-bit constants for "simple" constants
|
||
|
or when we'd need too many 32-bit stores, or when a 64-bit
|
||
|
constant is really required. */
|
||
|
if (vece == MO_64
|
||
|
|| (TCG_TARGET_REG_BITS == 64
|
||
|
&& (in_c == 0 || in_c == -1
|
||
|
|| !check_size_impl(oprsz, 4)))) {
|
||
|
t_64 = tcg_const_i64(s, in_c);
|
||
|
} else {
|
||
|
t_32 = tcg_const_i32(s, in_c);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* Implement inline if we picked an implementation size above. */
|
||
|
if (t_32) {
|
||
|
for (i = 0; i < oprsz; i += 4) {
|
||
|
tcg_gen_st_i32(s, t_32, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_i32(s, t_32);
|
||
|
goto done;
|
||
|
}
|
||
|
if (t_64) {
|
||
|
for (i = 0; i < oprsz; i += 8) {
|
||
|
tcg_gen_st_i64(s, t_64, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_i64(s, t_64);
|
||
|
goto done;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* Otherwise implement out of line. */
|
||
|
t_ptr = tcg_temp_new_ptr(s);
|
||
|
tcg_gen_addi_ptr(s, t_ptr, s->cpu_env, dofs);
|
||
|
t_desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, 0));
|
||
|
|
||
|
if (vece == MO_64) {
|
||
|
if (in_64) {
|
||
|
gen_helper_gvec_dup64(s, t_ptr, t_desc, in_64);
|
||
|
} else {
|
||
|
t_64 = tcg_const_i64(s, in_c);
|
||
|
gen_helper_gvec_dup64(s, t_ptr, t_desc, t_64);
|
||
|
tcg_temp_free_i64(s, t_64);
|
||
|
}
|
||
|
} else {
|
||
|
typedef void dup_fn(TCGContext *, TCGv_ptr, TCGv_i32, TCGv_i32);
|
||
|
static dup_fn * const fns[3] = {
|
||
|
gen_helper_gvec_dup8,
|
||
|
gen_helper_gvec_dup16,
|
||
|
gen_helper_gvec_dup32
|
||
|
};
|
||
|
|
||
|
if (in_32) {
|
||
|
fns[vece](s, t_ptr, t_desc, in_32);
|
||
|
} else {
|
||
|
t_32 = tcg_temp_new_i32(s);
|
||
|
if (in_64) {
|
||
|
tcg_gen_extrl_i64_i32(s, t_32, in_64);
|
||
|
} else if (vece == MO_8) {
|
||
|
tcg_gen_movi_i32(s, t_32, in_c & 0xff);
|
||
|
} else if (vece == MO_16) {
|
||
|
tcg_gen_movi_i32(s, t_32, in_c & 0xffff);
|
||
|
} else {
|
||
|
tcg_gen_movi_i32(s, t_32, in_c);
|
||
|
}
|
||
|
fns[vece](s, t_ptr, t_desc, t_32);
|
||
|
tcg_temp_free_i32(s, t_32);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
tcg_temp_free_ptr(s, t_ptr);
|
||
|
tcg_temp_free_i32(s, t_desc);
|
||
|
return;
|
||
|
|
||
|
done:
|
||
|
if (oprsz < maxsz) {
|
||
|
expand_clr(s, dofs + oprsz, maxsz - oprsz);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* Likewise, but with zero. */
|
||
|
static void expand_clr(TCGContext *s, uint32_t dofs, uint32_t maxsz)
|
||
|
{
|
||
|
do_dup(s, MO_8, dofs, maxsz, maxsz, NULL, NULL, 0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of two-operand operations using i32 elements. */
|
||
|
static void expand_2_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
|
||
|
void (*fni)(TCGContext *, TCGv_i32, TCGv_i32))
|
||
|
{
|
||
|
TCGv_i32 t0 = tcg_temp_new_i32(s);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += 4) {
|
||
|
tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
|
||
|
fni(s, t0, t0);
|
||
|
tcg_gen_st_i32(s, t0, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_i32(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
|
||
|
static void expand_3_i32(TCGContext *s, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, bool load_dest,
|
||
|
void (*fni)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32))
|
||
|
{
|
||
|
TCGv_i32 t0 = tcg_temp_new_i32(s);
|
||
|
TCGv_i32 t1 = tcg_temp_new_i32(s);
|
||
|
TCGv_i32 t2 = tcg_temp_new_i32(s);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += 4) {
|
||
|
tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
|
||
|
tcg_gen_ld_i32(s, t1, s->cpu_env, bofs + i);
|
||
|
if (load_dest) {
|
||
|
tcg_gen_ld_i32(s, t2, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
fni(s, t2, t0, t1);
|
||
|
tcg_gen_st_i32(s, t2, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_i32(s, t2);
|
||
|
tcg_temp_free_i32(s, t1);
|
||
|
tcg_temp_free_i32(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
|
||
|
static void expand_4_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
|
||
|
uint32_t cofs, uint32_t oprsz,
|
||
|
void (*fni)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32))
|
||
|
{
|
||
|
TCGv_i32 t0 = tcg_temp_new_i32(s);
|
||
|
TCGv_i32 t1 = tcg_temp_new_i32(s);
|
||
|
TCGv_i32 t2 = tcg_temp_new_i32(s);
|
||
|
TCGv_i32 t3 = tcg_temp_new_i32(s);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += 4) {
|
||
|
tcg_gen_ld_i32(s, t1, s->cpu_env, aofs + i);
|
||
|
tcg_gen_ld_i32(s, t2, s->cpu_env, bofs + i);
|
||
|
tcg_gen_ld_i32(s, t3, s->cpu_env, cofs + i);
|
||
|
fni(s, t0, t1, t2, t3);
|
||
|
tcg_gen_st_i32(s, t0, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_i32(s, t3);
|
||
|
tcg_temp_free_i32(s, t2);
|
||
|
tcg_temp_free_i32(s, t1);
|
||
|
tcg_temp_free_i32(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
|
||
|
static void expand_2_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
|
||
|
void (*fni)(TCGContext *, TCGv_i64, TCGv_i64))
|
||
|
{
|
||
|
TCGv_i64 t0 = tcg_temp_new_i64(s);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += 8) {
|
||
|
tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
|
||
|
fni(s, t0, t0);
|
||
|
tcg_gen_st_i64(s, t0, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_i64(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
|
||
|
static void expand_3_i64(TCGContext *s, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, bool load_dest,
|
||
|
void (*fni)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64))
|
||
|
{
|
||
|
TCGv_i64 t0 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t1 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t2 = tcg_temp_new_i64(s);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += 8) {
|
||
|
tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
|
||
|
tcg_gen_ld_i64(s, t1, s->cpu_env, bofs + i);
|
||
|
if (load_dest) {
|
||
|
tcg_gen_ld_i64(s, t2, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
fni(s, t2, t0, t1);
|
||
|
tcg_gen_st_i64(s, t2, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_i64(s, t2);
|
||
|
tcg_temp_free_i64(s, t1);
|
||
|
tcg_temp_free_i64(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
|
||
|
static void expand_4_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
|
||
|
uint32_t cofs, uint32_t oprsz,
|
||
|
void (*fni)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
|
||
|
{
|
||
|
TCGv_i64 t0 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t1 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t2 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t3 = tcg_temp_new_i64(s);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += 8) {
|
||
|
tcg_gen_ld_i64(s, t1, s->cpu_env, aofs + i);
|
||
|
tcg_gen_ld_i64(s, t2, s->cpu_env, bofs + i);
|
||
|
tcg_gen_ld_i64(s, t3, s->cpu_env, cofs + i);
|
||
|
fni(s, t0, t1, t2, t3);
|
||
|
tcg_gen_st_i64(s, t0, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_i64(s, t3);
|
||
|
tcg_temp_free_i64(s, t2);
|
||
|
tcg_temp_free_i64(s, t1);
|
||
|
tcg_temp_free_i64(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
|
||
|
static void expand_2_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t oprsz, uint32_t tysz, TCGType type,
|
||
|
void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec))
|
||
|
{
|
||
|
TCGv_vec t0 = tcg_temp_new_vec(s, type);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += tysz) {
|
||
|
tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
|
||
|
fni(s, vece, t0, t0);
|
||
|
tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_vec(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
|
||
|
static void expand_3_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz,
|
||
|
uint32_t tysz, TCGType type, bool load_dest,
|
||
|
void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
|
||
|
{
|
||
|
TCGv_vec t0 = tcg_temp_new_vec(s, type);
|
||
|
TCGv_vec t1 = tcg_temp_new_vec(s, type);
|
||
|
TCGv_vec t2 = tcg_temp_new_vec(s, type);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += tysz) {
|
||
|
tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
|
||
|
tcg_gen_ld_vec(s, t1, s->cpu_env, bofs + i);
|
||
|
if (load_dest) {
|
||
|
tcg_gen_ld_vec(s, t2, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
fni(s, vece, t2, t0, t1);
|
||
|
tcg_gen_st_vec(s, t2, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_vec(s, t2);
|
||
|
tcg_temp_free_vec(s, t1);
|
||
|
tcg_temp_free_vec(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand OPSZ bytes worth of four-operand operations using host vectors. */
|
||
|
static void expand_4_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t cofs, uint32_t oprsz,
|
||
|
uint32_t tysz, TCGType type,
|
||
|
void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec,
|
||
|
TCGv_vec, TCGv_vec))
|
||
|
{
|
||
|
TCGv_vec t0 = tcg_temp_new_vec(s, type);
|
||
|
TCGv_vec t1 = tcg_temp_new_vec(s, type);
|
||
|
TCGv_vec t2 = tcg_temp_new_vec(s, type);
|
||
|
TCGv_vec t3 = tcg_temp_new_vec(s, type);
|
||
|
uint32_t i;
|
||
|
|
||
|
for (i = 0; i < oprsz; i += tysz) {
|
||
|
tcg_gen_ld_vec(s, t1, s->cpu_env, aofs + i);
|
||
|
tcg_gen_ld_vec(s, t2, s->cpu_env, bofs + i);
|
||
|
tcg_gen_ld_vec(s, t3, s->cpu_env, cofs + i);
|
||
|
fni(s, vece, t0, t1, t2, t3);
|
||
|
tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_vec(s, t3);
|
||
|
tcg_temp_free_vec(s, t2);
|
||
|
tcg_temp_free_vec(s, t1);
|
||
|
tcg_temp_free_vec(s, t0);
|
||
|
}
|
||
|
|
||
|
/* Expand a vector two-operand operation. */
|
||
|
void tcg_gen_gvec_2(TCGContext *s, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs | aofs);
|
||
|
check_overlap_2(dofs, aofs, maxsz);
|
||
|
|
||
|
/* Recall that ARM SVE allows vector sizes that are not a power of 2.
|
||
|
Expand with successively smaller host vector sizes. The intent is
|
||
|
that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
|
||
|
/* ??? For maxsz > oprsz, the host may be able to use an opr-sized
|
||
|
operation, zeroing the balance of the register. We can then
|
||
|
use a max-sized store to implement the clearing without an extra
|
||
|
store operation. This is true for aarch64 and x86_64 hosts. */
|
||
|
|
||
|
if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
|
||
|
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
|
||
|
uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32);
|
||
|
expand_2_vec(s, g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv);
|
||
|
if (some == oprsz) {
|
||
|
goto done;
|
||
|
}
|
||
|
dofs += some;
|
||
|
aofs += some;
|
||
|
oprsz -= some;
|
||
|
maxsz -= some;
|
||
|
}
|
||
|
|
||
|
if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
|
||
|
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
|
||
|
expand_2_vec(s, g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv);
|
||
|
} else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
|
||
|
&& g->fniv && check_size_impl(oprsz, 8)
|
||
|
&& (!g->opc
|
||
|
|| tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
|
||
|
expand_2_vec(s, g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv);
|
||
|
} else if (g->fni8 && check_size_impl(oprsz, 8)) {
|
||
|
expand_2_i64(s, dofs, aofs, oprsz, g->fni8);
|
||
|
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
|
||
|
expand_2_i32(s, dofs, aofs, oprsz, g->fni4);
|
||
|
} else {
|
||
|
assert(g->fno != NULL);
|
||
|
tcg_gen_gvec_2_ool(s, dofs, aofs, oprsz, maxsz, g->data, g->fno);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
done:
|
||
|
if (oprsz < maxsz) {
|
||
|
expand_clr(s, dofs + oprsz, maxsz - oprsz);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* Expand a vector three-operand operation. */
|
||
|
void tcg_gen_gvec_3(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
|
||
|
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs | aofs | bofs);
|
||
|
check_overlap_3(dofs, aofs, bofs, maxsz);
|
||
|
|
||
|
/* Recall that ARM SVE allows vector sizes that are not a power of 2.
|
||
|
Expand with successively smaller host vector sizes. The intent is
|
||
|
that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
|
||
|
|
||
|
if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
|
||
|
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
|
||
|
uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32);
|
||
|
expand_3_vec(s, g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
|
||
|
g->load_dest, g->fniv);
|
||
|
if (some == oprsz) {
|
||
|
goto done;
|
||
|
}
|
||
|
dofs += some;
|
||
|
aofs += some;
|
||
|
bofs += some;
|
||
|
oprsz -= some;
|
||
|
maxsz -= some;
|
||
|
}
|
||
|
|
||
|
if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
|
||
|
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
|
||
|
expand_3_vec(s, g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
|
||
|
g->load_dest, g->fniv);
|
||
|
} else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
|
||
|
&& g->fniv && check_size_impl(oprsz, 8)
|
||
|
&& (!g->opc
|
||
|
|| tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
|
||
|
expand_3_vec(s, g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
|
||
|
g->load_dest, g->fniv);
|
||
|
} else if (g->fni8 && check_size_impl(oprsz, 8)) {
|
||
|
expand_3_i64(s, dofs, aofs, bofs, oprsz, g->load_dest, g->fni8);
|
||
|
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
|
||
|
expand_3_i32(s, dofs, aofs, bofs, oprsz, g->load_dest, g->fni4);
|
||
|
} else {
|
||
|
assert(g->fno != NULL);
|
||
|
tcg_gen_gvec_3_ool(s, dofs, aofs, bofs, oprsz, maxsz, g->data, g->fno);
|
||
|
}
|
||
|
|
||
|
done:
|
||
|
if (oprsz < maxsz) {
|
||
|
expand_clr(s, dofs + oprsz, maxsz - oprsz);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* Expand a vector four-operand operation. */
|
||
|
void tcg_gen_gvec_4(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
|
||
|
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
|
||
|
check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
|
||
|
|
||
|
/* Recall that ARM SVE allows vector sizes that are not a power of 2.
|
||
|
Expand with successively smaller host vector sizes. The intent is
|
||
|
that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
|
||
|
|
||
|
if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
|
||
|
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
|
||
|
uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32);
|
||
|
expand_4_vec(s, g->vece, dofs, aofs, bofs, cofs, some,
|
||
|
32, TCG_TYPE_V256, g->fniv);
|
||
|
if (some == oprsz) {
|
||
|
goto done;
|
||
|
}
|
||
|
dofs += some;
|
||
|
aofs += some;
|
||
|
bofs += some;
|
||
|
cofs += some;
|
||
|
oprsz -= some;
|
||
|
maxsz -= some;
|
||
|
}
|
||
|
|
||
|
if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
|
||
|
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
|
||
|
expand_4_vec(s, g->vece, dofs, aofs, bofs, cofs, oprsz,
|
||
|
16, TCG_TYPE_V128, g->fniv);
|
||
|
} else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
|
||
|
&& g->fniv && check_size_impl(oprsz, 8)
|
||
|
&& (!g->opc
|
||
|
|| tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
|
||
|
expand_4_vec(s, g->vece, dofs, aofs, bofs, cofs, oprsz,
|
||
|
8, TCG_TYPE_V64, g->fniv);
|
||
|
} else if (g->fni8 && check_size_impl(oprsz, 8)) {
|
||
|
expand_4_i64(s, dofs, aofs, bofs, cofs, oprsz, g->fni8);
|
||
|
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
|
||
|
expand_4_i32(s, dofs, aofs, bofs, cofs, oprsz, g->fni4);
|
||
|
} else {
|
||
|
assert(g->fno != NULL);
|
||
|
tcg_gen_gvec_4_ool(s, dofs, aofs, bofs, cofs,
|
||
|
oprsz, maxsz, g->data, g->fno);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
done:
|
||
|
if (oprsz < maxsz) {
|
||
|
expand_clr(s, dofs + oprsz, maxsz - oprsz);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Expand specific vector operations.
|
||
|
*/
|
||
|
|
||
|
static void vec_mov2(TCGContext *s, unsigned vece, TCGv_vec a, TCGv_vec b)
|
||
|
{
|
||
|
tcg_gen_mov_vec(s, a, b);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_mov(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen2 g = {
|
||
|
.fni8 = tcg_gen_mov_i64,
|
||
|
.fniv = vec_mov2,
|
||
|
.fno = gen_helper_gvec_mov,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
};
|
||
|
if (dofs != aofs) {
|
||
|
tcg_gen_gvec_2(s, dofs, aofs, oprsz, maxsz, &g);
|
||
|
} else {
|
||
|
check_size_align(oprsz, maxsz, dofs);
|
||
|
if (oprsz < maxsz) {
|
||
|
expand_clr(s, dofs + oprsz, maxsz - oprsz);
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_dup_i32(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
|
||
|
uint32_t maxsz, TCGv_i32 in)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs);
|
||
|
tcg_debug_assert(vece <= MO_32);
|
||
|
do_dup(s, vece, dofs, oprsz, maxsz, in, NULL, 0);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_dup_i64(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
|
||
|
uint32_t maxsz, TCGv_i64 in)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs);
|
||
|
tcg_debug_assert(vece <= MO_64);
|
||
|
do_dup(s, vece, dofs, oprsz, maxsz, NULL, in, 0);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_dup_mem(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
if (vece <= MO_32) {
|
||
|
TCGv_i32 in = tcg_temp_new_i32(s);
|
||
|
switch (vece) {
|
||
|
case MO_8:
|
||
|
tcg_gen_ld8u_i32(s, in, s->cpu_env, aofs);
|
||
|
break;
|
||
|
case MO_16:
|
||
|
tcg_gen_ld16u_i32(s, in, s->cpu_env, aofs);
|
||
|
break;
|
||
|
case MO_32:
|
||
|
tcg_gen_ld_i32(s, in, s->cpu_env, aofs);
|
||
|
break;
|
||
|
}
|
||
|
tcg_gen_gvec_dup_i32(s, vece, dofs, oprsz, maxsz, in);
|
||
|
tcg_temp_free_i32(s, in);
|
||
|
} else if (vece == MO_64) {
|
||
|
TCGv_i64 in = tcg_temp_new_i64(s);
|
||
|
tcg_gen_ld_i64(s, in, s->cpu_env, aofs);
|
||
|
tcg_gen_gvec_dup_i64(s, MO_64, dofs, oprsz, maxsz, in);
|
||
|
tcg_temp_free_i64(s, in);
|
||
|
} else {
|
||
|
/* 128-bit duplicate. */
|
||
|
/* ??? Dup to 256-bit vector. */
|
||
|
int i;
|
||
|
|
||
|
tcg_debug_assert(vece == 4);
|
||
|
tcg_debug_assert(oprsz >= 16);
|
||
|
if (TCG_TARGET_HAS_v128) {
|
||
|
TCGv_vec in = tcg_temp_new_vec(s, TCG_TYPE_V128);
|
||
|
|
||
|
tcg_gen_ld_vec(s, in, s->cpu_env, aofs);
|
||
|
for (i = 0; i < oprsz; i += 16) {
|
||
|
tcg_gen_st_vec(s, in, s->cpu_env, dofs + i);
|
||
|
}
|
||
|
tcg_temp_free_vec(s, in);
|
||
|
} else {
|
||
|
TCGv_i64 in0 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 in1 = tcg_temp_new_i64(s);
|
||
|
|
||
|
tcg_gen_ld_i64(s, in0, s->cpu_env, aofs);
|
||
|
tcg_gen_ld_i64(s, in1, s->cpu_env, aofs + 8);
|
||
|
for (i = 0; i < oprsz; i += 16) {
|
||
|
tcg_gen_st_i64(s, in0, s->cpu_env, dofs + i);
|
||
|
tcg_gen_st_i64(s, in1, s->cpu_env, dofs + i + 8);
|
||
|
}
|
||
|
tcg_temp_free_i64(s, in0);
|
||
|
tcg_temp_free_i64(s, in1);
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_dup64i(TCGContext *s, uint32_t dofs, uint32_t oprsz,
|
||
|
uint32_t maxsz, uint64_t x)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs);
|
||
|
do_dup(s, MO_64, dofs, oprsz, maxsz, NULL, NULL, x);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_dup32i(TCGContext *s, uint32_t dofs, uint32_t oprsz,
|
||
|
uint32_t maxsz, uint32_t x)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs);
|
||
|
do_dup(s, MO_32, dofs, oprsz, maxsz, NULL, NULL, x);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_dup16i(TCGContext *s, uint32_t dofs, uint32_t oprsz,
|
||
|
uint32_t maxsz, uint16_t x)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs);
|
||
|
do_dup(s, MO_16, dofs, oprsz, maxsz, NULL, NULL, x);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_dup8i(TCGContext *s, uint32_t dofs, uint32_t oprsz,
|
||
|
uint32_t maxsz, uint8_t x)
|
||
|
{
|
||
|
check_size_align(oprsz, maxsz, dofs);
|
||
|
do_dup(s, MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_not(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen2 g = {
|
||
|
.fni8 = tcg_gen_not_i64,
|
||
|
.fniv = tcg_gen_not_vec,
|
||
|
.fno = gen_helper_gvec_not,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
};
|
||
|
tcg_gen_gvec_2(s, dofs, aofs, oprsz, maxsz, &g);
|
||
|
}
|
||
|
|
||
|
/* Perform a vector addition using normal addition and a mask. The mask
|
||
|
should be the sign bit of each lane. This 6-operation form is more
|
||
|
efficient than separate additions when there are 4 or more lanes in
|
||
|
the 64-bit operation. */
|
||
|
static void gen_addv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
|
||
|
{
|
||
|
TCGv_i64 t1 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t2 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t3 = tcg_temp_new_i64(s);
|
||
|
|
||
|
tcg_gen_andc_i64(s, t1, a, m);
|
||
|
tcg_gen_andc_i64(s, t2, b, m);
|
||
|
tcg_gen_xor_i64(s, t3, a, b);
|
||
|
tcg_gen_add_i64(s, d, t1, t2);
|
||
|
tcg_gen_and_i64(s, t3, t3, m);
|
||
|
tcg_gen_xor_i64(s, d, d, t3);
|
||
|
|
||
|
tcg_temp_free_i64(s, t1);
|
||
|
tcg_temp_free_i64(s, t2);
|
||
|
tcg_temp_free_i64(s, t3);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_add8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 m = tcg_const_i64(s, dup_const(MO_8, 0x80));
|
||
|
gen_addv_mask(s, d, a, b, m);
|
||
|
tcg_temp_free_i64(s, m);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_add16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 m = tcg_const_i64(s, dup_const(MO_16, 0x8000));
|
||
|
gen_addv_mask(s, d, a, b, m);
|
||
|
tcg_temp_free_i64(s, m);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_add32_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 t1 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t2 = tcg_temp_new_i64(s);
|
||
|
|
||
|
tcg_gen_andi_i64(s, t1, a, ~0xffffffffull);
|
||
|
tcg_gen_add_i64(s, t2, a, b);
|
||
|
tcg_gen_add_i64(s, t1, t1, b);
|
||
|
tcg_gen_deposit_i64(s, d, t1, t2, 0, 32);
|
||
|
|
||
|
tcg_temp_free_i64(s, t1);
|
||
|
tcg_temp_free_i64(s, t2);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_add(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen3 g[4] = {
|
||
|
{ .fni8 = tcg_gen_vec_add8_i64,
|
||
|
.fniv = tcg_gen_add_vec,
|
||
|
.fno = gen_helper_gvec_add8,
|
||
|
.opc = INDEX_op_add_vec,
|
||
|
.vece = MO_8 },
|
||
|
{ .fni8 = tcg_gen_vec_add16_i64,
|
||
|
.fniv = tcg_gen_add_vec,
|
||
|
.fno = gen_helper_gvec_add16,
|
||
|
.opc = INDEX_op_add_vec,
|
||
|
.vece = MO_16 },
|
||
|
{ .fni4 = tcg_gen_add_i32,
|
||
|
.fniv = tcg_gen_add_vec,
|
||
|
.fno = gen_helper_gvec_add32,
|
||
|
.opc = INDEX_op_add_vec,
|
||
|
.vece = MO_32 },
|
||
|
{ .fni8 = tcg_gen_add_i64,
|
||
|
.fniv = tcg_gen_add_vec,
|
||
|
.fno = gen_helper_gvec_add64,
|
||
|
.opc = INDEX_op_add_vec,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
.vece = MO_64 },
|
||
|
};
|
||
|
|
||
|
tcg_debug_assert(vece <= MO_64);
|
||
|
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||
|
}
|
||
|
|
||
|
/* Perform a vector subtraction using normal subtraction and a mask.
|
||
|
Compare gen_addv_mask above. */
|
||
|
static void gen_subv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
|
||
|
{
|
||
|
TCGv_i64 t1 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t2 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t3 = tcg_temp_new_i64(s);
|
||
|
|
||
|
tcg_gen_or_i64(s, t1, a, m);
|
||
|
tcg_gen_andc_i64(s, t2, b, m);
|
||
|
tcg_gen_eqv_i64(s, t3, a, b);
|
||
|
tcg_gen_sub_i64(s, d, t1, t2);
|
||
|
tcg_gen_and_i64(s, t3, t3, m);
|
||
|
tcg_gen_xor_i64(s, d, d, t3);
|
||
|
|
||
|
tcg_temp_free_i64(s, t1);
|
||
|
tcg_temp_free_i64(s, t2);
|
||
|
tcg_temp_free_i64(s, t3);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_sub8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 m = tcg_const_i64(s, dup_const(MO_8, 0x80));
|
||
|
gen_subv_mask(s, d, a, b, m);
|
||
|
tcg_temp_free_i64(s, m);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_sub16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 m = tcg_const_i64(s, dup_const(MO_16, 0x8000));
|
||
|
gen_subv_mask(s, d, a, b, m);
|
||
|
tcg_temp_free_i64(s, m);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_sub32_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 t1 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t2 = tcg_temp_new_i64(s);
|
||
|
|
||
|
tcg_gen_andi_i64(s, t1, b, ~0xffffffffull);
|
||
|
tcg_gen_sub_i64(s, t2, a, b);
|
||
|
tcg_gen_sub_i64(s, t1, a, t1);
|
||
|
tcg_gen_deposit_i64(s, d, t1, t2, 0, 32);
|
||
|
|
||
|
tcg_temp_free_i64(s, t1);
|
||
|
tcg_temp_free_i64(s, t2);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_sub(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen3 g[4] = {
|
||
|
{ .fni8 = tcg_gen_vec_sub8_i64,
|
||
|
.fniv = tcg_gen_sub_vec,
|
||
|
.fno = gen_helper_gvec_sub8,
|
||
|
.opc = INDEX_op_sub_vec,
|
||
|
.vece = MO_8 },
|
||
|
{ .fni8 = tcg_gen_vec_sub16_i64,
|
||
|
.fniv = tcg_gen_sub_vec,
|
||
|
.fno = gen_helper_gvec_sub16,
|
||
|
.opc = INDEX_op_sub_vec,
|
||
|
.vece = MO_16 },
|
||
|
{ .fni4 = tcg_gen_sub_i32,
|
||
|
.fniv = tcg_gen_sub_vec,
|
||
|
.fno = gen_helper_gvec_sub32,
|
||
|
.opc = INDEX_op_sub_vec,
|
||
|
.vece = MO_32 },
|
||
|
{ .fni8 = tcg_gen_sub_i64,
|
||
|
.fniv = tcg_gen_sub_vec,
|
||
|
.fno = gen_helper_gvec_sub64,
|
||
|
.opc = INDEX_op_sub_vec,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
.vece = MO_64 },
|
||
|
};
|
||
|
|
||
|
tcg_debug_assert(vece <= MO_64);
|
||
|
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||
|
}
|
||
|
|
||
|
/* Perform a vector negation using normal negation and a mask.
|
||
|
Compare gen_subv_mask above. */
|
||
|
static void gen_negv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
|
||
|
{
|
||
|
TCGv_i64 t2 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t3 = tcg_temp_new_i64(s);
|
||
|
|
||
|
tcg_gen_andc_i64(s, t3, m, b);
|
||
|
tcg_gen_andc_i64(s, t2, b, m);
|
||
|
tcg_gen_sub_i64(s, d, m, t2);
|
||
|
tcg_gen_xor_i64(s, d, d, t3);
|
||
|
|
||
|
tcg_temp_free_i64(s, t2);
|
||
|
tcg_temp_free_i64(s, t3);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_neg8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 m = tcg_const_i64(s, dup_const(MO_8, 0x80));
|
||
|
gen_negv_mask(s, d, b, m);
|
||
|
tcg_temp_free_i64(s, m);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_neg16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 m = tcg_const_i64(s, dup_const(MO_16, 0x8000));
|
||
|
gen_negv_mask(s, d, b, m);
|
||
|
tcg_temp_free_i64(s, m);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_vec_neg32_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 b)
|
||
|
{
|
||
|
TCGv_i64 t1 = tcg_temp_new_i64(s);
|
||
|
TCGv_i64 t2 = tcg_temp_new_i64(s);
|
||
|
|
||
|
tcg_gen_andi_i64(s, t1, b, ~0xffffffffull);
|
||
|
tcg_gen_neg_i64(s, t2, b);
|
||
|
tcg_gen_neg_i64(s, t1, t1);
|
||
|
tcg_gen_deposit_i64(s, d, t1, t2, 0, 32);
|
||
|
|
||
|
tcg_temp_free_i64(s, t1);
|
||
|
tcg_temp_free_i64(s, t2);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_neg(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen2 g[4] = {
|
||
|
{ .fni8 = tcg_gen_vec_neg8_i64,
|
||
|
.fniv = tcg_gen_neg_vec,
|
||
|
.fno = gen_helper_gvec_neg8,
|
||
|
.opc = INDEX_op_neg_vec,
|
||
|
.vece = MO_8 },
|
||
|
{ .fni8 = tcg_gen_vec_neg16_i64,
|
||
|
.fniv = tcg_gen_neg_vec,
|
||
|
.fno = gen_helper_gvec_neg16,
|
||
|
.opc = INDEX_op_neg_vec,
|
||
|
.vece = MO_16 },
|
||
|
{ .fni4 = tcg_gen_neg_i32,
|
||
|
.fniv = tcg_gen_neg_vec,
|
||
|
.fno = gen_helper_gvec_neg32,
|
||
|
.opc = INDEX_op_neg_vec,
|
||
|
.vece = MO_32 },
|
||
|
{ .fni8 = tcg_gen_neg_i64,
|
||
|
.fniv = tcg_gen_neg_vec,
|
||
|
.fno = gen_helper_gvec_neg64,
|
||
|
.opc = INDEX_op_neg_vec,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
.vece = MO_64 },
|
||
|
};
|
||
|
|
||
|
tcg_debug_assert(vece <= MO_64);
|
||
|
tcg_gen_gvec_2(s, dofs, aofs, oprsz, maxsz, &g[vece]);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_and(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen3 g = {
|
||
|
.fni8 = tcg_gen_and_i64,
|
||
|
.fniv = tcg_gen_and_vec,
|
||
|
.fno = gen_helper_gvec_and,
|
||
|
.opc = INDEX_op_and_vec,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
};
|
||
|
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_or(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen3 g = {
|
||
|
.fni8 = tcg_gen_or_i64,
|
||
|
.fniv = tcg_gen_or_vec,
|
||
|
.fno = gen_helper_gvec_or,
|
||
|
.opc = INDEX_op_or_vec,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
};
|
||
|
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_xor(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen3 g = {
|
||
|
.fni8 = tcg_gen_xor_i64,
|
||
|
.fniv = tcg_gen_xor_vec,
|
||
|
.fno = gen_helper_gvec_xor,
|
||
|
.opc = INDEX_op_xor_vec,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
};
|
||
|
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_andc(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen3 g = {
|
||
|
.fni8 = tcg_gen_andc_i64,
|
||
|
.fniv = tcg_gen_andc_vec,
|
||
|
.fno = gen_helper_gvec_andc,
|
||
|
.opc = INDEX_op_andc_vec,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
};
|
||
|
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
|
||
|
}
|
||
|
|
||
|
void tcg_gen_gvec_orc(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||
|
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||
|
{
|
||
|
static const GVecGen3 g = {
|
||
|
.fni8 = tcg_gen_orc_i64,
|
||
|
.fniv = tcg_gen_orc_vec,
|
||
|
.fno = gen_helper_gvec_orc,
|
||
|
.opc = INDEX_op_orc_vec,
|
||
|
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||
|
};
|
||
|
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
|
||
|
}
|