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unicorn/qemu/target/riscv/cpu_helper.c

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target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
/*
* RISC-V CPU helpers for qemu.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
#define RISCV_DEBUG_INTERRUPT 0
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return 0;
#else
return env->priv;
#endif
}
#ifndef CONFIG_USER_ONLY
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
target_ulong pending = atomic_read(&env->mip) & env->mie;
target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie);
target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie);
target_ulong irqs = (pending & ~env->mideleg & -mie) |
(pending & env->mideleg & -sie);
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
return EXCP_NONE; /* indicates no pending interrupt */
}
}
#endif
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_HARD) {
RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
CPURISCVState *env = &cpu->env;
int interruptno = riscv_cpu_local_irq_pending(env);
if (interruptno >= 0) {
cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno;
riscv_cpu_do_interrupt(cs);
return true;
}
}
#endif
return false;
}
#if !defined(CONFIG_USER_ONLY)
RISC-V: Allow interrupt controllers to claim interrupts We can't allow the supervisor to control SEIP as this would allow the supervisor to clear a pending external interrupt which will result in lost a interrupt in the case a PLIC is attached. The SEIP bit must be hardware controlled when a PLIC is attached. This logic was previously hard-coded so SEIP was always masked even if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts so that the PLIC can register control of SEIP. In the case of models without a PLIC (spike), the SEIP bit remains software controlled. This interface allows for hardware control of supervisor timer and software interrupts by other interrupt controller models. Backports commit e3e7039cc24ecf47d81c091e8bb04552d6564ad8 from qemu
2019-03-20 03:47:35 +00:00
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
if (env->miclaim & interrupts) {
return -1;
} else {
env->miclaim |= interrupts;
return 0;
}
}
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
/* iothread_mutex must be held */
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
CPURISCVState *env = &cpu->env;
uint32_t old, new, cmp = atomic_read(&env->mip);
do {
old = cmp;
new = (old & ~mask) | (value & mask);
cmp = atomic_cmpxchg(&env->mip, old, new);
} while (old != cmp);
RISC-V: Change local interrupts from edge to level This effectively changes riscv_cpu_update_mip from edge to level. i.e. cpu_interrupt or cpu_reset_interrupt are called regardless of the current interrupt level. Fixes WFI doesn't return when a IPI is issued: - https://github.com/riscv/riscv-qemu/issues/132 To test: 1) Apply RISC-V Linux CPU hotplug patch: - http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html 2) Enable CONFIG_CPU_HOTPLUG in linux .config 3) Try to offline and online cpus: echo 1 > /sys/devices/system/cpu/cpu2/online echo 0 > /sys/devices/system/cpu/cpu2/online echo 1 > /sys/devices/system/cpu/cpu2/online Backports commit d26f5a423438e579d3ff0ca35e44edb966a36233 from qemu
2019-03-20 03:49:02 +00:00
if (new) {
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
RISC-V: Change local interrupts from edge to level This effectively changes riscv_cpu_update_mip from edge to level. i.e. cpu_interrupt or cpu_reset_interrupt are called regardless of the current interrupt level. Fixes WFI doesn't return when a IPI is issued: - https://github.com/riscv/riscv-qemu/issues/132 To test: 1) Apply RISC-V Linux CPU hotplug patch: - http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html 2) Enable CONFIG_CPU_HOTPLUG in linux .config 3) Try to offline and online cpus: echo 1 > /sys/devices/system/cpu/cpu2/online echo 0 > /sys/devices/system/cpu/cpu2/online echo 1 > /sys/devices/system/cpu/cpu2/online Backports commit d26f5a423438e579d3ff0ca35e44edb966a36233 from qemu
2019-03-20 03:49:02 +00:00
} else {
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
return old;
}
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
g_assert_not_reached();
}
if (newpriv == PRV_H) {
newpriv = PRV_U;
}
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
env->priv = newpriv;
RISC-V: Clear load reservations on context switch and SC This prevents a load reservation from being placed in one context/process, then being used in another, resulting in an SC succeeding incorrectly and breaking atomics. Backports commit c13b169f1a3dd158d6c75727cdc388f95988db39 from qemu
2019-08-08 21:12:21 +00:00
/*
* Clear the load reservation - otherwise a reservation placed in one
* context/process can be used by another, resulting in an SC succeeding
* incorrectly. Version 2.2 of the ISA specification explicitly requires
* this behaviour, while later revisions say that the kernel "should" use
* an SC instruction to force the yielding of a load reservation on a
* preemptive context switch. As a result, do both.
*/
env->load_res = -1;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
}
/* get_physical_address - get the physical address for this virtual address
*
* Do a page table walk to obtain the physical address corresponding to a
* virtual address. Returns 0 if the translation was successful
*
* Adapted from Spike's mmu_t::translate and mmu_t::walk
*
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
int access_type, int mmu_idx)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
* (riscv_cpu_do_interrupt) is correct */
int mode = mmu_idx;
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
}
if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
}
*prot = 0;
target_ulong base;
int levels, ptidxbits, ptesize, vm, sum;
int mxr = get_field(env->mstatus, MSTATUS_MXR);
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
base = get_field(env->satp, SATP_PPN) << PGSHIFT;
sum = get_field(env->mstatus, MSTATUS_SUM);
vm = get_field(env->satp, SATP_MODE);
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
case VM_1_10_SV39:
levels = 3; ptidxbits = 9; ptesize = 8; break;
case VM_1_10_SV48:
levels = 4; ptidxbits = 9; ptesize = 8; break;
case VM_1_10_SV57:
levels = 5; ptidxbits = 9; ptesize = 8; break;
case VM_1_10_MBARE:
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
default:
g_assert_not_reached();
}
} else {
base = env->sptbr << PGSHIFT;
sum = !get_field(env->mstatus, MSTATUS_PUM);
vm = get_field(env->mstatus, MSTATUS_VM);
switch (vm) {
case VM_1_09_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
case VM_1_09_SV39:
levels = 3; ptidxbits = 9; ptesize = 8; break;
case VM_1_09_SV48:
levels = 4; ptidxbits = 9; ptesize = 8; break;
case VM_1_09_MBARE:
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
default:
g_assert_not_reached();
}
}
target/riscv: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Backports commit 3109cd98a6c0c618189b38a83a8aa29cb20acbce from qemu
2019-06-12 15:58:56 +00:00
CPUState *cs = env_cpu(env);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
int va_bits = PGSHIFT + levels * ptidxbits;
target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask;
if (masked_msbs != 0 && masked_msbs != mask) {
return TRANSLATE_FAIL;
}
int ptshift = (levels - 1) * ptidxbits;
int i;
#if !TCG_OVERSIZED_GUEST
restart:
#endif
for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
target_ulong idx = (addr >> (PGSHIFT + ptshift)) &
((1 << ptidxbits) - 1);
/* check that physical address of PTE is legal */
target_ulong pte_addr = base + idx * ptesize;
RISC-V: Check PMP during Page Table Walks The PMP should be checked when doing a page table walk, and report access fault exception if the to-be-read PTE failed the PMP check. Backports commit 1f447aec787bfbbd078afccae44fc4c92acb4fed from qemu
2019-08-08 20:54:43 +00:00
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
1 << MMU_DATA_LOAD, PRV_S)) {
return TRANSLATE_PMP_FAIL;
}
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#if defined(TARGET_RISCV32)
target_ulong pte = ldl_phys(cs->as, pte_addr);
#elif defined(TARGET_RISCV64)
target_ulong pte = ldq_phys(cs->as, pte_addr);
#endif
target_ulong ppn = pte >> PTE_PPN_SHIFT;
if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
return TRANSLATE_FAIL;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) {
/* Reserved leaf PTE flags: PTE_W + PTE_X */
return TRANSLATE_FAIL;
} else if ((pte & PTE_U) && ((mode != PRV_U) &&
(!sum || access_type == MMU_INST_FETCH))) {
/* User PTE flags when not U mode and mstatus.SUM is not set,
or the access type is an instruction fetch */
return TRANSLATE_FAIL;
} else if (!(pte & PTE_U) && (mode != PRV_S)) {
/* Supervisor PTE flags when not S mode */
return TRANSLATE_FAIL;
} else if (ppn & ((1ULL << ptshift) - 1)) {
/* Misaligned PPN */
return TRANSLATE_FAIL;
} else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) ||
((pte & PTE_X) && mxr))) {
/* Read access check failed */
return TRANSLATE_FAIL;
} else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) {
/* Write access check failed */
return TRANSLATE_FAIL;
} else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
/* Fetch access check failed */
return TRANSLATE_FAIL;
} else {
/* if necessary, set accessed and dirty bits. */
target_ulong updated_pte = pte | PTE_A |
(access_type == MMU_DATA_STORE ? PTE_D : 0);
/* Page table updates need to be atomic with MTTCG enabled */
if (updated_pte != pte) {
/*
* - if accessed or dirty bits need updating, and the PTE is
* in RAM, then we do so atomically with a compare and swap.
* - if the PTE is in IO space or ROM, then it can't be updated
* and we return TRANSLATE_FAIL.
* - if the PTE changed by the time we went to update it, then
* it is no longer valid and we must re-walk the page table.
*/
MemoryRegion *mr;
hwaddr l = sizeof(target_ulong), addr1;
mr = address_space_translate(cs->as, pte_addr,
&addr1, &l, false);
if (memory_region_is_ram(mr)) {
target_ulong *pte_pa =
qemu_map_ram_ptr(env->uc, mr->ram_block, addr1);
#if TCG_OVERSIZED_GUEST
/* MTTCG is not enabled on oversized TCG guests so
* page table updates do not need to be atomic */
*pte_pa = pte = updated_pte;
#else
target_ulong old_pte =
atomic_cmpxchg(pte_pa, pte, updated_pte);
if (old_pte != pte) {
goto restart;
} else {
pte = updated_pte;
}
#endif
} else {
/* misconfigured PTE in ROM (AD bits are not preset) or
* PTE is in IO space and can't be updated atomically */
return TRANSLATE_FAIL;
}
}
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
*physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
*prot |= PAGE_READ;
}
if ((pte & PTE_X)) {
*prot |= PAGE_EXEC;
}
/* add write permission on stores or if the page is already dirty,
so that we TLB miss on later writes to update the dirty bit */
if ((pte & PTE_W) &&
(access_type == MMU_DATA_STORE || (pte & PTE_D))) {
*prot |= PAGE_WRITE;
}
return TRANSLATE_SUCCESS;
}
}
return TRANSLATE_FAIL;
}
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
RISC-V: Raise access fault exceptions on PMP violations Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Backports commit 635b0b0ea39a13d1a3df932452e5728aebbb3f6e from qemu
2019-08-08 20:50:55 +00:00
MMUAccessType access_type, bool pmp_violation)
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
{
target/riscv: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Backports commit 3109cd98a6c0c618189b38a83a8aa29cb20acbce from qemu
2019-06-12 15:58:56 +00:00
CPUState *cs = env_cpu(env);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
int page_fault_exceptions =
(env->priv_ver >= PRIV_VERSION_1_10_0) &&
RISC-V: Raise access fault exceptions on PMP violations Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Backports commit 635b0b0ea39a13d1a3df932452e5728aebbb3f6e from qemu
2019-08-08 20:50:55 +00:00
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
!pmp_violation;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = page_fault_exceptions ?
RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT;
break;
case MMU_DATA_LOAD:
cs->exception_index = page_fault_exceptions ?
RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT;
break;
case MMU_DATA_STORE:
cs->exception_index = page_fault_exceptions ?
RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
break;
default:
g_assert_not_reached();
}
env->badaddr = address;
}
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
hwaddr phys_addr;
int prot;
int mmu_idx = cpu_mmu_index(&cpu->env, false);
if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
return -1;
}
return phys_addr;
}
target/riscv: Implement riscv_cpu_unassigned_access This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Backports commit cbf5827693addaff4e4d2102afedbf078a204eb2 from qemu
2019-08-08 20:45:11 +00:00
void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
bool is_exec, int unused, unsigned size)
{
RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
CPURISCVState *env = &cpu->env;
if (is_write) {
cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
} else {
cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
}
env->badaddr = addr;
riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());
}
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr)
{
RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
CPURISCVState *env = &cpu->env;
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
break;
case MMU_DATA_LOAD:
cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS;
break;
case MMU_DATA_STORE:
cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS;
break;
default:
g_assert_not_reached();
}
env->badaddr = addr;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
#endif
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
{
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
#ifndef CONFIG_USER_ONLY
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
CPURISCVState *env = &cpu->env;
hwaddr pa = 0;
int prot;
RISC-V: Raise access fault exceptions on PMP violations Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Backports commit 635b0b0ea39a13d1a3df932452e5728aebbb3f6e from qemu
2019-08-08 20:50:55 +00:00
bool pmp_violation = false;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
int ret = TRANSLATE_FAIL;
RISC-V: Check for the effective memory privilege mode during PMP checks The current PMP check function checks for env->priv which is not the effective memory privilege mode. For example, mstatus.MPRV could be set while executing in M-Mode, and in that case the privilege mode for the PMP check should be S-Mode rather than M-Mode (in env->priv) if mstatus.MPP == PRV_S. This patch passes the effective memory privilege mode to the PMP check. Functions that call the PMP check should pass the correct memory privilege mode after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists). Backports commit cc0fdb298517ce56c770803447f8b02a90271152 from qemu
2019-08-08 20:52:56 +00:00
int mode = mmu_idx;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
RISC-V: Check for the effective memory privilege mode during PMP checks The current PMP check function checks for env->priv which is not the effective memory privilege mode. For example, mstatus.MPRV could be set while executing in M-Mode, and in that case the privilege mode for the PMP check should be S-Mode rather than M-Mode (in env->priv) if mstatus.MPP == PRV_S. This patch passes the effective memory privilege mode to the PMP check. Functions that call the PMP check should pass the correct memory privilege mode after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists). Backports commit cc0fdb298517ce56c770803447f8b02a90271152 from qemu
2019-08-08 20:52:56 +00:00
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
}
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
qemu_log_mask(CPU_LOG_MMU,
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
" prot %d\n", __func__, address, ret, pa, prot);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
RISC-V: Only Check PMP if MMU translation succeeds The current implementation unnecessarily checks for PMP even if MMU translation failed. This may trigger a wrong PMP access exception instead of a page exception. For example, the very first instruction fetched after the first satp write in S-Mode will trigger a PMP access fault instead of an instruction fetch page fault. This patch prioritises MMU exceptions over PMP exceptions and only checks for PMP if MMU translation succeeds. This patch is required for future commits that properly report PMP exception violations if PTW succeeds. Backports commit e0f8fa72deba7ac7a7ae06ba25e6498aaad93ace from qemu
2019-08-08 20:48:56 +00:00
(ret == TRANSLATE_SUCCESS) &&
RISC-V: Fix a PMP check with the correct access size The PMP check should be of the memory access size rather than TARGET_PAGE_SIZE. Backports commit db21e6f72721996ddf1948c35a8ee35238089da4 from qemu
2019-08-08 20:57:00 +00:00
!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
RISC-V: Check PMP during Page Table Walks The PMP should be checked when doing a page table walk, and report access fault exception if the to-be-read PTE failed the PMP check. Backports commit 1f447aec787bfbbd078afccae44fc4c92acb4fed from qemu
2019-08-08 20:54:43 +00:00
ret = TRANSLATE_PMP_FAIL;
}
if (ret == TRANSLATE_PMP_FAIL) {
RISC-V: Raise access fault exceptions on PMP violations Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Backports commit 635b0b0ea39a13d1a3df932452e5728aebbb3f6e from qemu
2019-08-08 20:50:55 +00:00
pmp_violation = true;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
}
if (ret == TRANSLATE_SUCCESS) {
tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
return true;
} else if (probe) {
return false;
} else {
RISC-V: Raise access fault exceptions on PMP violations Section 3.6 in RISC-V v1.10 privilege specification states that PMP violations report "access exceptions." The current PMP implementation has a bug which wrongly reports "page exceptions" on PMP violations. This patch fixes this bug by reporting the correct PMP access exceptions trap values. Backports commit 635b0b0ea39a13d1a3df932452e5728aebbb3f6e from qemu
2019-08-08 20:50:55 +00:00
raise_mmu_exception(env, address, access_type, pmp_violation);
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
riscv_raise_exception(env, cs->exception_index, retaddr);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
}
#else
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
switch (access_type) {
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
case MMU_INST_FETCH:
cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
break;
case MMU_DATA_LOAD:
cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
break;
case MMU_DATA_STORE:
cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
break;
}
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
cpu_loop_exit_restore(cs, retaddr);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#endif
}
/*
* Handle Traps
*
* Adapted from Spike's processor_t::take_trap.
*
*/
void riscv_cpu_do_interrupt(CPUState *cs)
{
#if !defined(CONFIG_USER_ONLY)
RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
CPURISCVState *env = &cpu->env;
RISC-V: Add support for vectored interrupts If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-20 03:51:52 +00:00
/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
* so we mask off the MSB and separate into trap type and cause.
*/
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
target_ulong deleg = async ? env->mideleg : env->medeleg;
target_ulong tval = 0;
static const int ecall_cause_map[] = {
[PRV_U] = RISCV_EXCP_U_ECALL,
[PRV_S] = RISCV_EXCP_S_ECALL,
[PRV_H] = RISCV_EXCP_H_ECALL,
[PRV_M] = RISCV_EXCP_M_ECALL
};
if (!async) {
/* set tval to badaddr for traps with address information */
switch (cause) {
case RISCV_EXCP_INST_ADDR_MIS:
case RISCV_EXCP_INST_ACCESS_FAULT:
case RISCV_EXCP_LOAD_ADDR_MIS:
case RISCV_EXCP_STORE_AMO_ADDR_MIS:
case RISCV_EXCP_LOAD_ACCESS_FAULT:
case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
case RISCV_EXCP_INST_PAGE_FAULT:
case RISCV_EXCP_LOAD_PAGE_FAULT:
case RISCV_EXCP_STORE_PAGE_FAULT:
tval = env->badaddr;
break;
default:
break;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
}
RISC-V: Add support for vectored interrupts If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-20 03:51:52 +00:00
/* ecall is dispatched as one cause so translate based on mode */
if (cause == RISCV_EXCP_U_ECALL) {
assert(env->priv <= 3);
cause = ecall_cause_map[env->priv];
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
}
}
RISC-V: Add support for vectored interrupts If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-20 03:51:52 +00:00
if (RISCV_DEBUG_INTERRUPT) {
qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, "
"epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n",
env->mhartid, async ? "intr" : "trap",
(async ? riscv_intr_names : riscv_excp_names)[cause],
env->pc, tval);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
}
RISC-V: Add support for vectored interrupts If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-20 03:51:52 +00:00
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
/* handle the trap in S-mode */
target_ulong s = env->mstatus;
s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
target/riscv: Improve the scause logic No functional change, just making the code easier to read. Backports commit 16fdb8ff64374ed51b246437e13043039a8eb9f9 from qemu
2019-05-28 23:14:29 +00:00
env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
RISC-V: Add support for vectored interrupts If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-20 03:51:52 +00:00
env->sepc = env->pc;
env->sbadaddr = tval;
env->pc = (env->stvec >> 2 << 2) +
((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
riscv_cpu_set_mode(env, PRV_S);
} else {
RISC-V: Add support for vectored interrupts If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-20 03:51:52 +00:00
/* handle the trap in M-mode */
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
target_ulong s = env->mstatus;
s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
RISC-V: Add support for vectored interrupts If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-20 03:51:52 +00:00
env->mcause = cause | ~(((target_ulong)-1) >> async);
env->mepc = env->pc;
env->mbadaddr = tval;
env->pc = (env->mtvec >> 2 << 2) +
((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
riscv_cpu_set_mode(env, PRV_M);
}
RISC-V: Update load reservation comment in do_interrupt Backports commit d9360e96885dbd69ce4aa925d1701c7a10cf54ae from qemu
2019-03-20 03:53:34 +00:00
/* NOTE: it is not necessary to yield load reservations here. It is only
* necessary for an SC from "another hart" to cause a load reservation
* to be yielded. Refer to the memory consistency model section of the
* RISC-V ISA Specification.
*/
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#endif
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
}
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