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i386: define the AMD 'amd-ssbd' CPUID feature bit

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AMD future CPUs expose _two_ ways to utilize the Intel equivalant
of the Speculative Store Bypass Disable. The first is via
the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
is via the SPEC_CTRL MSR (0x48). The document titled:
124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf

gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.

A copy of this document is available at
https://bugzilla.kernel.org/show_bug.cgi?id=199889

Anyhow, this means that on future AMD CPUs there will be _two_ ways to
deal with SSBD.

Backports commit a764f3f7197f4d7ad8fe8424269933de912224cb from qemu
This commit is contained in:
Konrad Rzeszutek Wilk 2018-07-03 00:24:08 -04:00 committed by Lioncash
parent bffd8c6244
commit 0023d048aa
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 1 deletions
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2
qemu/target/i386/cpu.c
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@ -909,7 +909,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"ibpb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, "virt-ssbd", NULL, NULL,
"amd-ssbd", "virt-ssbd", NULL, NULL,
NULL, NULL, NULL, NULL,
},
0x80000008,