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target-mips: support CP0.Config4.AE bit

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The read-only Config4.AE bit set denotes extended 10 bits ASID.

Backports commit a0c8060841f2d56fb3504292c18522b957972e4c from qemu
This commit is contained in:
Paul Burton 2018-02-25 03:49:31 -05:00 committed by Lioncash
parent ba4dcc8c2f
commit 002b392a15
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 3 additions and 1 deletions
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1
qemu/target-mips/cpu.h
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@ -469,6 +469,7 @@ struct CPUMIPSState {
int32_t CP0_Config4_rw_bitmask;
#define CP0C4_M 31
#define CP0C4_IE 29
#define CP0C4_AE 28
#define CP0C4_KScrExist 16
#define CP0C4_MMUExtDef 14
#define CP0C4_FTLBPageSize 8

3
qemu/target-mips/translate.c
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@ -20434,7 +20434,8 @@ void cpu_state_reset(CPUMIPSState *env)
if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
}
env->CP0_EntryHi_ASID_mask = 0xff;
env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ?
0x3ff : 0xff;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
/* vectored interrupts not implemented, timer on int 7,
no performance counters. */