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target/arm: Adjust sve_exception_el

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Check for EL3 before testing CPTR_EL3.EZ. Return 0 when the exception
should be routed via AdvSIMDFPAccessTrap. Mirror the structure of
CheckSVEEnabled more closely.

Fixes: 5be5e8eda78

Backports commit 60eed0869d68b91eff71cc0a0facb01983726a5d from qemu
This commit is contained in:
Richard Henderson 2018-10-08 11:13:18 -04:00 committed by Lioncash
parent 1081e5e7a4
commit 00fc5d43fd
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 46 additions and 50 deletions
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96
qemu/target/arm/helper.c
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@ -3825,67 +3825,63 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
/* Return the exception level to which SVE-disabled exceptions should /* Return the exception level to which exceptions should be taken
* be taken, or 0 if SVE is enabled. * via SVEAccessTrap. If an exception should be routed through
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
* take care of raising that exception.
* C.f. the ARM pseudocode function CheckSVEEnabled.
*/ */
static int sve_exception_el(CPUARMState *env) static int sve_exception_el(CPUARMState *env)
{ {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
unsigned current_el = arm_current_el(env); unsigned current_el = arm_current_el(env);
/* The CPACR.ZEN controls traps to EL1: if (current_el <= 1) {
* 0, 2 : trap EL0 and EL1 accesses bool disabled = false;
* 1 : trap only EL0 accesses
* 3 : trap no accesses /* The CPACR.ZEN controls traps to EL1:
* 0, 2 : trap EL0 and EL1 accesses
* 1 : trap only EL0 accesses
* 3 : trap no accesses
*/
if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
disabled = true;
} else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
disabled = current_el == 0;
}
if (disabled) {
/* route_to_el2 */
return (arm_feature(env, ARM_FEATURE_EL2)
&& !arm_is_secure(env)
&& (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1);
}
/* Check CPACR.FPEN. */
if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
disabled = true;
} else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
disabled = current_el == 0;
}
if (disabled) {
return 0;
}
}
/* CPTR_EL2. Since TZ and TFP are positive,
* they will be zero when EL2 is not present.
*/ */
switch (extract32(env->cp15.cpacr_el1, 16, 2)) { if (current_el <= 2 && !arm_is_secure_below_el3(env)) {
default: if (env->cp15.cptr_el[2] & CPTR_TZ) {
if (current_el <= 1) { return 2;
/* Trap to PL1, which might be EL1 or EL3 */
if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
return 3;
}
return 1;
} }
break; if (env->cp15.cptr_el[2] & CPTR_TFP) {
case 1: return 0;
if (current_el == 0) {
return 1;
} }
break;
case 3:
break;
} }
/* Similarly for CPACR.FPEN, after having checked ZEN. */ /* CPTR_EL3. Since EZ is negative we must check for EL3. */
switch (extract32(env->cp15.cpacr_el1, 20, 2)) { if (arm_feature(env, ARM_FEATURE_EL3)
default: && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
if (current_el <= 1) {
if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
return 3;
}
return 1;
}
break;
case 1:
if (current_el == 0) {
return 1;
}
break;
case 3:
break;
}
/* CPTR_EL2. Check both TZ and TFP. */
if (current_el <= 2
&& (env->cp15.cptr_el[2] & (CPTR_TFP | CPTR_TZ))
&& !arm_is_secure_below_el3(env)) {
return 2;
}
/* CPTR_EL3. Check both EZ and TFP. */
if (!(env->cp15.cptr_el[3] & CPTR_EZ)
|| (env->cp15.cptr_el[3] & CPTR_TFP)) {
return 3; return 3;
} }
#endif #endif