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target/arm: Define ID_AA64ZFR0_EL1

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Given that the only field defined for this new register may only
be 0, we don't actually need to change anything except the name.

Backports commit 9516d7725ec1deaa6ef5ccc5a26d005650d6c524 from qemu
This commit is contained in:
Richard Henderson 2018-10-08 11:10:55 -04:00 committed by Lioncash
parent d82046cafc
commit 1081e5e7a4
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 1 deletions
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3
qemu/target/arm/helper.c
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@ -4380,7 +4380,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
PL1_R, 0, NULL, 0 },
{ "ID_AA64PFR3_EL1_RESERVED", 0,0,4, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0,},
{ "ID_AA64PFR4_EL1_RESERVED", 0,0,4, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST,
{ "ID_AA64ZFR0_EL1", 0,0,4, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST,
/* At present, only SVEver == 0 is defined anyway. */
PL1_R, 0, NULL, 0 },
{ "ID_AA64PFR5_EL1_RESERVED", 0,0,4, 3,0,5, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL1_R, 0, NULL, 0 },