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Removed hardcoded CP0C3_ULRI (#1098)

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* activate CP0C3_ULRI for CONFIG3, mips

* updated with mips patches

* updated with mips patches

* remove hardcoded config3

* git ignore vscode

* fix spacing issue and turn on floating point

Backports most of commit 24f55a7973278f20f0de21b904851d99d4716263 from
unicorn. Ignores internal core modifications, as this would be
special-casing non-upstreamed behavior.
This commit is contained in:
kj.xwings.l 2019-08-08 20:05:56 -04:00 committed by Lioncash
parent deeeb1d0b9
commit 038b4f3345
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
8 changed files with 33 additions and 6 deletions
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4
bindings/dotnet/UnicornManaged/Const/Mips.fs
View file

@ -158,7 +158,9 @@ module Mips =
let UC_MIPS_REG_MPL0 = 134
let UC_MIPS_REG_MPL1 = 135
let UC_MIPS_REG_MPL2 = 136
let UC_MIPS_REG_ENDING = 137
let UC_MIPS_REG_CP0_CONFIG3 = 137
let UC_MIPS_REG_CP0_USERLOCAL = 138
let UC_MIPS_REG_ENDING = 139
let UC_MIPS_REG_ZERO = 2
let UC_MIPS_REG_AT = 3
let UC_MIPS_REG_V0 = 4

4
bindings/go/unicorn/mips_const.go
View file

@ -153,7 +153,9 @@ const (
MIPS_REG_MPL0 = 134
MIPS_REG_MPL1 = 135
MIPS_REG_MPL2 = 136
MIPS_REG_ENDING = 137
MIPS_REG_CP0_CONFIG3 = 137
MIPS_REG_CP0_USERLOCAL = 138
MIPS_REG_ENDING = 139
MIPS_REG_ZERO = 2
MIPS_REG_AT = 3
MIPS_REG_V0 = 4

4
bindings/java/unicorn/MipsConst.java
View file

@ -155,7 +155,9 @@ public interface MipsConst {
public static final int UC_MIPS_REG_MPL0 = 134;
public static final int UC_MIPS_REG_MPL1 = 135;
public static final int UC_MIPS_REG_MPL2 = 136;
public static final int UC_MIPS_REG_ENDING = 137;
public static final int UC_MIPS_REG_CP0_CONFIG3 = 137;
public static final int UC_MIPS_REG_CP0_USERLOCAL = 138;
public static final int UC_MIPS_REG_ENDING = 139;
public static final int UC_MIPS_REG_ZERO = 2;
public static final int UC_MIPS_REG_AT = 3;
public static final int UC_MIPS_REG_V0 = 4;

4
bindings/pascal/unicorn/MipsConst.pas
View file

@ -156,7 +156,9 @@ const
UC_MIPS_REG_MPL0 = 134;
UC_MIPS_REG_MPL1 = 135;
UC_MIPS_REG_MPL2 = 136;
UC_MIPS_REG_ENDING = 137;
UC_MIPS_REG_CP0_CONFIG3 = 137;
UC_MIPS_REG_CP0_USERLOCAL = 138;
UC_MIPS_REG_ENDING = 139;
UC_MIPS_REG_ZERO = 2;
UC_MIPS_REG_AT = 3;
UC_MIPS_REG_V0 = 4;

4
bindings/python/unicorn/mips_const.py
View file

@ -151,7 +151,9 @@ UC_MIPS_REG_P2 = 133
UC_MIPS_REG_MPL0 = 134
UC_MIPS_REG_MPL1 = 135
UC_MIPS_REG_MPL2 = 136
UC_MIPS_REG_ENDING = 137
UC_MIPS_REG_CP0_CONFIG3 = 137
UC_MIPS_REG_CP0_USERLOCAL = 138
UC_MIPS_REG_ENDING = 139
UC_MIPS_REG_ZERO = 2
UC_MIPS_REG_AT = 3
UC_MIPS_REG_V0 = 4

4
bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb
View file

@ -153,7 +153,9 @@ module UnicornEngine
UC_MIPS_REG_MPL0 = 134
UC_MIPS_REG_MPL1 = 135
UC_MIPS_REG_MPL2 = 136
UC_MIPS_REG_ENDING = 137
UC_MIPS_REG_CP0_CONFIG3 = 137
UC_MIPS_REG_CP0_USERLOCAL = 138
UC_MIPS_REG_ENDING = 139
UC_MIPS_REG_ZERO = 2
UC_MIPS_REG_AT = 3
UC_MIPS_REG_V0 = 4

3
include/unicorn/mips.h
View file

@ -175,6 +175,9 @@ typedef enum UC_MIPS_REG {
UC_MIPS_REG_MPL1,
UC_MIPS_REG_MPL2,
UC_MIPS_REG_CP0_CONFIG3,
UC_MIPS_REG_CP0_USERLOCAL,
UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers
// alias registers

12
qemu/target/mips/unicorn.c
View file

@ -83,6 +83,12 @@ int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int cou
case UC_MIPS_REG_PC:
*(mipsreg_t *)value = state->active_tc.PC;
break;
case UC_MIPS_REG_CP0_CONFIG3:
*(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.CP0_Config3;
break;
case UC_MIPS_REG_CP0_USERLOCAL:
*(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.CP0_UserLocal;
break;
}
}
}
@ -110,6 +116,12 @@ int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
uc->quit_request = true;
uc_emu_stop(uc);
break;
case UC_MIPS_REG_CP0_CONFIG3:
MIPS_CPU(uc, mycpu)->env.CP0_Config3 = *(mipsreg_t *)value;
break;
case UC_MIPS_REG_CP0_USERLOCAL:
MIPS_CPU(uc, mycpu)->env.active_tc.CP0_UserLocal = *(mipsreg_t *)value;
break;
}
}
}