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target/arm: Convert Neon fp VMUL, VMLA, VMLS 3-reg-same insns to decodetree
Convert the Neon integer VMUL, VMLA, and VMLS 3-reg-same inssn to decodetree. We don't have a gvec helper for multiply-accumulate, so VMLA and VMLS need a loop function do_3same_fp(). This takes a reads_vd parameter to do_3same_fp() which tells it to load the old value into vd before calling the callback function, in the same way that the do_vfp_3op_sp() and do_vfp_3op_dp() functions in translate-vfp.inc.c work. (The only uses in this patch pass reads_vd == true, but later commits will use reads_vd == false.) This conversion fixes in passing an underdecoding for VMUL Backports commit 8aa71ead912ca0a9c0d29b74e0976f91952f950a from qemu
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2527e76926
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qemu/target/arm
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@ -180,5 +180,8 @@ VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
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VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
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VPADD_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0
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VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
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VMLA_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
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VMLS_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp
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VMUL_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
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VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0
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VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0
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@ -1040,6 +1040,56 @@ DO_3SAME_PAIR(VPADD, padd_u)
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DO_3SAME_VQDMULH(VQDMULH, qdmulh)
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DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
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static bool do_3same_fp(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn,
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bool reads_vd)
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{
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/*
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* FP operations handled elementwise 32 bits at a time.
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* If reads_vd is true then the old value of Vd will be
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* loaded before calling the callback function. This is
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* used for multiply-accumulate type operations.
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*/
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TCGv_i32 tmp, tmp2;
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int pass;
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vn | a->vm) & 0x10)) {
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return false;
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}
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if ((a->vn | a->vm | a->vd) & a->q) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
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for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
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tmp = neon_load_reg(s, a->vn, pass);
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tmp2 = neon_load_reg(s, a->vm, pass);
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if (reads_vd) {
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TCGv_i32 tmp_rd = neon_load_reg(s, a->vd, pass);
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fn(tcg_ctx, tmp_rd, tmp, tmp2, fpstatus);
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neon_store_reg(s, a->vd, pass, tmp_rd);
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tcg_temp_free_i32(tcg_ctx, tmp);
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} else {
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fn(tcg_ctx, tmp, tmp, tmp2, fpstatus);
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neon_store_reg(s, a->vd, pass, tmp);
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}
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tcg_temp_free_i32(tcg_ctx, tmp2);
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}
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tcg_temp_free_ptr(tcg_ctx, fpstatus);
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return true;
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}
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/*
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* For all the functions using this macro, size == 1 means fp16,
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* which is an architecture extension we don't implement yet.
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@ -1067,6 +1117,38 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
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DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s)
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DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s)
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DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s)
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DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s)
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/*
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* For all the functions using this macro, size == 1 means fp16,
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* which is an architecture extension we don't implement yet.
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*/
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#define DO_3S_FP(INSN,FUNC,READS_VD) \
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static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
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{ \
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if (a->size != 0) { \
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/* TODO fp16 support */ \
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return false; \
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} \
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return do_3same_fp(s, a, FUNC, READS_VD); \
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}
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static void gen_VMLA_fp_3s(TCGContext *s, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
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TCGv_ptr fpstatus)
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{
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gen_helper_vfp_muls(s, vn, vn, vm, fpstatus);
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gen_helper_vfp_adds(s, vd, vd, vn, fpstatus);
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}
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static void gen_VMLS_fp_3s(TCGContext *s, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm,
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TCGv_ptr fpstatus)
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{
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gen_helper_vfp_muls(s, vn, vn, vm, fpstatus);
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gen_helper_vfp_subs(s, vd, vd, vn, fpstatus);
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}
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DO_3S_FP(VMLA, gen_VMLA_fp_3s, true)
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DO_3S_FP(VMLS, gen_VMLS_fp_3s, true)
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static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
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{
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@ -5559,6 +5559,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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case NEON_3R_VPADD_VQRDMLAH:
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case NEON_3R_VQDMULH_VQRDMULH:
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case NEON_3R_FLOAT_ARITH:
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case NEON_3R_FLOAT_MULTIPLY:
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/* Already handled by decodetree */
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return 1;
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}
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@ -5605,22 +5606,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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tmp = neon_load_reg(s, rn, pass);
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tmp2 = neon_load_reg(s, rm, pass);
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switch (op) {
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case NEON_3R_FLOAT_MULTIPLY:
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{
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TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
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gen_helper_vfp_muls(tcg_ctx, tmp, tmp, tmp2, fpstatus);
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if (!u) {
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tcg_temp_free_i32(tcg_ctx, tmp2);
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tmp2 = neon_load_reg(s, rd, pass);
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if (size == 0) {
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gen_helper_vfp_adds(tcg_ctx, tmp, tmp, tmp2, fpstatus);
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} else {
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gen_helper_vfp_subs(tcg_ctx, tmp, tmp2, tmp, fpstatus);
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}
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}
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tcg_temp_free_ptr(tcg_ctx, fpstatus);
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break;
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}
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case NEON_3R_FLOAT_CMP:
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{
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TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);
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