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target/mips: Clean up handling of CP0 register 16

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Clean up handling of CP0 register 16.

Backports commit 433efb4cca1d942b6849be953ea166b492e9bb59 from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 23:14:39 -05:00 committed by Lioncash
parent e54d2617a1
commit 04de1c3a5e
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 32 additions and 31 deletions
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3
qemu/target/mips/cpu.h
View file

@ -374,7 +374,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG16__CONFIG3 3
#define CP0_REG16__CONFIG4 4
#define CP0_REG16__CONFIG5 5
#define CP0_REG00__CONFIG7 7
#define CP0_REG16__CONFIG6 6
#define CP0_REG16__CONFIG7 7
/* CP0 Register 17 */
#define CP0_REG17__LLADDR 0
#define CP0_REG17__MAAR 1

60
qemu/target/mips/translate.c
View file

@ -7325,36 +7325,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
case 0:
case CP0_REG16__CONFIG:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
case 1:
case CP0_REG16__CONFIG1:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
case 2:
case CP0_REG16__CONFIG2:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
case 3:
case CP0_REG16__CONFIG3:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
case 4:
case CP0_REG16__CONFIG4:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
case 5:
case CP0_REG16__CONFIG5:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
case 6:
case CP0_REG16__CONFIG6:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
case 7:
case CP0_REG16__CONFIG7:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@ -8051,45 +8051,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
case 0:
case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 1:
case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
case 2:
case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 3:
case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 4:
case CP0_REG16__CONFIG4:
gen_helper_mtc0_config4(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
case 5:
case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
case 6:
case CP0_REG16__CONFIG6:
/* ignored */
register_name = "Config6";
break;
case 7:
case CP0_REG16__CONFIG7:
/* ignored */
register_name = "Config7";
break;
@ -8794,36 +8794,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
case 0:
case CP0_REG16__CONFIG:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
case 1:
case CP0_REG16__CONFIG1:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
case 2:
case CP0_REG16__CONFIG2:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
case 3:
case CP0_REG16__CONFIG3:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
case 4:
case CP0_REG16__CONFIG4:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
case 5:
case CP0_REG16__CONFIG5:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
case 6:
case CP0_REG16__CONFIG6:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
case 7:
case CP0_REG16__CONFIG7:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@ -9507,33 +9507,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
case 0:
case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 1:
case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
case 2:
case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 3:
case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
case 4:
case CP0_REG16__CONFIG4:
/* currently ignored */
register_name = "Config4";
break;
case 5:
case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */