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target/mips: Clean up handling of CP0 register 15
Clean up handling of CP0 register 15. Backports commit 4466cd49e53d3a4418a0f27ea9ff335fd9aed180 from qemu
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parent
41133450de
commit
e54d2617a1
qemu/target/mips
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@ -366,6 +366,7 @@ typedef struct mips_def_t mips_def_t;
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#define CP0_REG15__EBASE 1
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#define CP0_REG15__CDMMBASE 2
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#define CP0_REG15__CMGCRBASE 3
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#define CP0_REG15__BEVVA 4
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/* CP0 Register 16 */
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#define CP0_REG16__CONFIG 0
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#define CP0_REG16__CONFIG1 1
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@ -7302,17 +7302,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_15:
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switch (sel) {
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case 0:
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case CP0_REG15__PRID:
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gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PRid));
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register_name = "PRid";
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break;
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case 1:
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case CP0_REG15__EBASE:
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check_insn(ctx, ISA_MIPS32R2);
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tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EBase));
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tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
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register_name = "EBase";
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break;
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case 3:
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case CP0_REG15__CMGCRBASE:
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check_insn(ctx, ISA_MIPS32R2);
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CP0_CHECK(ctx->cmgcr);
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tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
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@ -8036,11 +8036,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_15:
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switch (sel) {
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case 0:
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case CP0_REG15__PRID:
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/* ignored */
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register_name = "PRid";
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break;
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case 1:
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case CP0_REG15__EBASE:
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check_insn(ctx, ISA_MIPS32R2);
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gen_helper_mtc0_ebase(tcg_ctx, tcg_ctx->cpu_env, arg);
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register_name = "EBase";
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@ -8773,16 +8773,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_15:
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switch (sel) {
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case 0:
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case CP0_REG15__PRID:
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gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PRid));
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register_name = "PRid";
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break;
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case 1:
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case CP0_REG15__EBASE:
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check_insn(ctx, ISA_MIPS32R2);
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tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EBase));
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register_name = "EBase";
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break;
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case 3:
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case CP0_REG15__CMGCRBASE:
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check_insn(ctx, ISA_MIPS32R2);
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CP0_CHECK(ctx->cmgcr);
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tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
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@ -9492,11 +9492,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_15:
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switch (sel) {
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case 0:
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case CP0_REG15__PRID:
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/* ignored */
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register_name = "PRid";
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break;
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case 1:
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case CP0_REG15__EBASE:
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check_insn(ctx, ISA_MIPS32R2);
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gen_helper_mtc0_ebase(tcg_ctx, tcg_ctx->cpu_env, arg);
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register_name = "EBase";
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