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target/riscv: support vector extension csr

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The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.

Backports 8e3a1f18871e0ea251b95561fe1ec5a9bc896c4a from qemu
This commit is contained in:
LIU Zhiwei 2021-02-26 02:25:55 -05:00 committed by Lioncash
parent bff31d8822
commit 0554e79ad1
2 changed files with 90 additions and 0 deletions
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15
qemu/target/riscv/cpu_bits.h
View file

@ -29,6 +29,14 @@
#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
/* Vector Fixed-Point round model */
#define FSR_VXRM_SHIFT 9
#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT)
/* Vector Fixed-Point saturation flag */
#define FSR_VXSAT_SHIFT 8
#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT)
/* Control and Status Registers */
/* User Trap Setup */
@ -48,6 +56,13 @@
#define CSR_FRM 0x002
#define CSR_FCSR 0x003
/* User Vector CSRs */
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01

75
qemu/target/riscv/csr.c
View file

@ -45,6 +45,10 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static int fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
/* loose check condition for fcsr in vector extension */
if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
return 0;
}
if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
@ -52,6 +56,14 @@ static int fs(CPURISCVState *env, int csrno)
return 0;
}
static int vs(CPURISCVState *env, int csrno)
{
if (env->misa & RVV) {
return 0;
}
return -1;
}
static int ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
@ -146,6 +158,10 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
if (vs(env, csrno) >= 0) {
*val |= (env->vxrm << FSR_VXRM_SHIFT)
| (env->vxsat << FSR_VXSAT_SHIFT);
}
return 0;
}
@ -158,10 +174,62 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
if (vs(env, csrno) >= 0) {
env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
}
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return 0;
}
static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vtype;
return 0;
}
static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vl;
return 0;
}
static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vxrm;
return 0;
}
static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
{
env->vxrm = val;
return 0;
}
static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vxsat;
return 0;
}
static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
{
env->vxsat = val;
return 0;
}
static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vstart;
return 0;
}
static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
{
env->vstart = val;
return 0;
}
/* User Timers and Counters */
static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
{
@ -1185,6 +1253,13 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FRM] = { fs, read_frm, write_frm },
[CSR_FCSR] = { fs, read_fcsr, write_fcsr },
/* Vector CSRs */
[CSR_VSTART] = { vs, read_vstart, write_vstart },
[CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { vs, read_vxrm, write_vxrm },
[CSR_VL] = { vs, read_vl },
[CSR_VTYPE] = { vs, read_vtype },
/* User Timers and Counters */
[CSR_CYCLE] = { ctr, read_instret },
[CSR_INSTRET] = { ctr, read_instret },