mirror of
https://github.com/yuzu-emu/unicorn.git
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cpu: Generify CPU init functions
Backports commits 2994fd96d986578a342f2342501b4ad30f6d0a85, 701e3c78ce45fa630ffc6826c4b9a4218954bc7f, and d1853231c60d16af78cf4d1608d043614bfbac0b from qemuu
This commit is contained in:
parent
ce1831bfb4
commit
074865ff98
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_aarch64
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#define cpu_abort cpu_abort_aarch64
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#define cpu_address_space_init cpu_address_space_init_aarch64
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#define cpu_arm_init cpu_arm_init_aarch64
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#define cpu_breakpoint_insert cpu_breakpoint_insert_aarch64
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#define cpu_breakpoint_remove cpu_breakpoint_remove_aarch64
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_aarch64
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_aarch64eb
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#define cpu_abort cpu_abort_aarch64eb
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#define cpu_address_space_init cpu_address_space_init_aarch64eb
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#define cpu_arm_init cpu_arm_init_aarch64eb
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#define cpu_breakpoint_insert cpu_breakpoint_insert_aarch64eb
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#define cpu_breakpoint_remove cpu_breakpoint_remove_aarch64eb
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_aarch64eb
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_arm
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#define cpu_abort cpu_abort_arm
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#define cpu_address_space_init cpu_address_space_init_arm
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#define cpu_arm_init cpu_arm_init_arm
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#define cpu_breakpoint_insert cpu_breakpoint_insert_arm
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#define cpu_breakpoint_remove cpu_breakpoint_remove_arm
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_arm
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_armeb
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#define cpu_abort cpu_abort_armeb
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#define cpu_address_space_init cpu_address_space_init_armeb
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#define cpu_arm_init cpu_arm_init_armeb
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#define cpu_breakpoint_insert cpu_breakpoint_insert_armeb
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#define cpu_breakpoint_remove cpu_breakpoint_remove_armeb
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_armeb
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@ -262,7 +262,6 @@ symbols = (
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'cptype_valid',
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'cpu_abort',
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'cpu_address_space_init',
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'cpu_arm_init',
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'cpu_breakpoint_insert',
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'cpu_breakpoint_remove',
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'cpu_breakpoint_remove_all',
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@ -4121,7 +4120,6 @@ sparc_symbols = (
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'cpu_raise_exception_ra',
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'cpu_set_cwp',
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'cpu_sparc_exec',
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'cpu_sparc_init',
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'cpu_sparc_set_id',
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'dump_mmu',
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'helper_check_align',
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@ -22,9 +22,9 @@
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static int tosa_init(struct uc_struct *uc, MachineState *machine)
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{
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if (uc->mode & UC_MODE_MCLASS) {
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uc->cpu = (CPUState *)cpu_arm_init(uc, "cortex-m3");
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uc->cpu = cpu_init(uc, "cortex-m3");
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} else {
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uc->cpu = (CPUState *)cpu_arm_init(uc, "cortex-a15");
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uc->cpu = cpu_init(uc, "cortex-a15");
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}
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return 0;
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@ -79,7 +79,7 @@ static int machvirt_init(struct uc_struct *uc, MachineState *machine)
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}
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cpuobj = object_new(uc, object_class_get_name(oc));
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uc->cpu = (CPUState *)cpuobj;
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uc->cpu = CPU(cpuobj);
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object_property_set_bool(uc, cpuobj, true, "realized", NULL);
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}
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@ -22,16 +22,18 @@ static int dummy_m68k_init(struct uc_struct *uc, MachineState *machine)
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const char *cpu_model = machine->cpu_model;
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CPUM68KState *env;
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if (!cpu_model)
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if (!cpu_model) {
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cpu_model = "cfv4e";
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}
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env = cpu_init(uc, cpu_model);
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if (!env) {
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uc->cpu = cpu_init(uc, cpu_model);
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if (!uc->cpu) {
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fprintf(stderr, "Unable to find m68k CPU definition\n");
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return -1;
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}
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/* Initialize CPU registers. */
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env = uc->cpu->env_ptr;
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env->vbr = 0;
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env->pc = 0;
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@ -46,8 +46,8 @@ static int leon3_generic_hw_init(struct uc_struct *uc, MachineState *machine)
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cpu_model = "LEON3";
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}
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cpu = cpu_sparc_init(uc, cpu_model);
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uc->cpu = CPU(cpu);
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uc->cpu = cpu_init(uc, cpu_model);
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cpu = SPARC_CPU(uc, uc->cpu);
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if (cpu == NULL) {
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fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
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return -1;
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@ -39,10 +39,12 @@ static int sun4u_init(struct uc_struct *uc, MachineState *machine)
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const char *cpu_model = machine->cpu_model;
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SPARCCPU *cpu;
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if (cpu_model == NULL)
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if (cpu_model == NULL) {
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cpu_model = "Sun UltraSparc IV";
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}
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cpu = cpu_sparc_init(uc, cpu_model);
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uc->cpu = cpu_init(uc, cpu_model);
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cpu = SPARC_CPU(uc, uc->cpu);
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if (cpu == NULL) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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return -1;
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_m68k
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#define cpu_abort cpu_abort_m68k
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#define cpu_address_space_init cpu_address_space_init_m68k
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#define cpu_arm_init cpu_arm_init_m68k
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#define cpu_breakpoint_insert cpu_breakpoint_insert_m68k
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#define cpu_breakpoint_remove cpu_breakpoint_remove_m68k
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_m68k
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_mips
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#define cpu_abort cpu_abort_mips
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#define cpu_address_space_init cpu_address_space_init_mips
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#define cpu_arm_init cpu_arm_init_mips
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#define cpu_breakpoint_insert cpu_breakpoint_insert_mips
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#define cpu_breakpoint_remove cpu_breakpoint_remove_mips
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_mips
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_mips64
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#define cpu_abort cpu_abort_mips64
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#define cpu_address_space_init cpu_address_space_init_mips64
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#define cpu_arm_init cpu_arm_init_mips64
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#define cpu_breakpoint_insert cpu_breakpoint_insert_mips64
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#define cpu_breakpoint_remove cpu_breakpoint_remove_mips64
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_mips64
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#define cptype_valid cptype_valid_mips64el
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#define cpu_abort cpu_abort_mips64el
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#define cpu_address_space_init cpu_address_space_init_mips64el
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#define cpu_arm_init cpu_arm_init_mips64el
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#define cpu_breakpoint_insert cpu_breakpoint_insert_mips64el
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#define cpu_breakpoint_remove cpu_breakpoint_remove_mips64el
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_mips64el
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_mipsel
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#define cpu_abort cpu_abort_mipsel
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#define cpu_address_space_init cpu_address_space_init_mipsel
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#define cpu_arm_init cpu_arm_init_mipsel
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#define cpu_breakpoint_insert cpu_breakpoint_insert_mipsel
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#define cpu_breakpoint_remove cpu_breakpoint_remove_mipsel
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_mipsel
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_powerpc
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#define cpu_abort cpu_abort_powerpc
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#define cpu_address_space_init cpu_address_space_init_powerpc
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#define cpu_arm_init cpu_arm_init_powerpc
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#define cpu_breakpoint_insert cpu_breakpoint_insert_powerpc
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#define cpu_breakpoint_remove cpu_breakpoint_remove_powerpc
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_powerpc
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_sparc
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#define cpu_abort cpu_abort_sparc
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#define cpu_address_space_init cpu_address_space_init_sparc
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#define cpu_arm_init cpu_arm_init_sparc
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#define cpu_breakpoint_insert cpu_breakpoint_insert_sparc
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#define cpu_breakpoint_remove cpu_breakpoint_remove_sparc
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_sparc
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@ -3064,7 +3063,6 @@
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#define cpu_raise_exception_ra cpu_raise_exception_ra_sparc
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#define cpu_set_cwp cpu_set_cwp_sparc
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#define cpu_sparc_exec cpu_sparc_exec_sparc
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#define cpu_sparc_init cpu_sparc_init_sparc
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#define cpu_sparc_set_id cpu_sparc_set_id_sparc
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#define dump_mmu dump_mmu_sparc
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#define helper_check_align helper_check_align_sparc
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@ -256,7 +256,6 @@
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#define cptype_valid cptype_valid_sparc64
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#define cpu_abort cpu_abort_sparc64
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#define cpu_address_space_init cpu_address_space_init_sparc64
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#define cpu_arm_init cpu_arm_init_sparc64
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#define cpu_breakpoint_insert cpu_breakpoint_insert_sparc64
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#define cpu_breakpoint_remove cpu_breakpoint_remove_sparc64
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_sparc64
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#define cpu_raise_exception_ra cpu_raise_exception_ra_sparc64
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#define cpu_set_cwp cpu_set_cwp_sparc64
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#define cpu_sparc_exec cpu_sparc_exec_sparc64
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#define cpu_sparc_init cpu_sparc_init_sparc64
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#define cpu_sparc_set_id cpu_sparc_set_id_sparc64
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#define dump_mmu dump_mmu_sparc64
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#define helper_check_align helper_check_align_sparc64
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@ -840,7 +840,6 @@ bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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MemTxAttrs *attrs);
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ARMCPU *cpu_arm_init(struct uc_struct *uc, const char *cpu_model);
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target_ulong do_arm_semihosting(CPUARMState *env);
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void aarch64_sync_32_to_64(CPUARMState *env);
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void aarch64_sync_64_to_32(CPUARMState *env);
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return unmasked || pstate_unmasked;
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}
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static inline CPUARMState *cpu_init(struct uc_struct *uc, const char *cpu_model)
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{
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ARMCPU *cpu = cpu_arm_init(uc, cpu_model);
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if (cpu) {
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return &cpu->env;
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}
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return NULL;
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}
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#ifdef TARGET_ARM
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#define cpu_init(uc, cpu_model) cpu_generic_init(uc, TYPE_ARM_CPU, cpu_model)
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#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
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#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
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@ -4733,11 +4733,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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}
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}
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ARMCPU *cpu_arm_init(struct uc_struct *uc, const char *cpu_model)
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{
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return ARM_CPU(uc, cpu_generic_init(uc, TYPE_ARM_CPU, cpu_model));
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}
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void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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{
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#if 0
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@ -3201,37 +3201,6 @@ out:
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return cpu;
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}
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CPUX86State *cpu_x86_init_user(struct uc_struct *uc, const char *cpu_model)
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{
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Error *error = NULL;
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X86CPU *cpu;
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cpu = cpu_x86_create(uc, cpu_model, &error);
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if (error) {
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goto error;
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}
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object_property_set_int(uc, OBJECT(cpu), CPU(cpu)->cpu_index, "apic-id",
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&error);
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if (error) {
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goto error;
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}
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object_property_set_bool(uc, OBJECT(cpu), true, "realized", &error);
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if (error) {
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goto error;
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}
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return &cpu->env;
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error:
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error_free(error);
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if (cpu != NULL) {
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object_unref(uc, OBJECT(cpu));
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}
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return NULL;
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}
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static void x86_cpu_cpudef_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
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{
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X86CPUDefinition *cpudef = data;
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@ -4144,6 +4113,12 @@ static int x86_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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goto out;
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}*/
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object_property_set_int(uc, OBJECT(cpu), CPU(cpu)->cpu_index, "apic-id",
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&local_err);
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if (local_err) {
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goto out;
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}
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if (cpu->apic_id == UNASSIGNED_APIC_ID) {
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error_setg(errp, "apic-id property was not initialized properly");
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return -1;
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@ -1520,10 +1520,12 @@ uint64_t cpu_get_tsc(CPUX86State *env);
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#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
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CPUX86State *cpu_x86_init_user(struct uc_struct *uc, const char *cpu_model);
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#define cpu_init cpu_x86_init_user
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#ifdef TARGET_I386
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#define cpu_init(uc, cpu_model) cpu_generic_init(uc, TYPE_X86_CPU, cpu_model)
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#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
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#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
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#define cpu_signal_handler cpu_x86_signal_handler
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#endif
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@ -191,7 +191,6 @@ int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void m68k_tcg_init(struct uc_struct *uc);
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M68kCPU *cpu_m68k_init(struct uc_struct *uc, const char *cpu_model);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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@ -522,14 +521,10 @@ enum {
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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static inline CPUM68KState *cpu_init(struct uc_struct *uc, const char *cpu_model)
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{
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M68kCPU *cpu = cpu_m68k_init(uc, cpu_model);
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if (cpu == NULL) {
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return NULL;
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}
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return &cpu->env;
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}
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#define cpu_init(uc, cpu_model) cpu_generic_init(uc, TYPE_M68K_CPU, cpu_model)
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#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
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#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
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#define cpu_signal_handler cpu_m68k_signal_handler
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#define cpu_list m68k_cpu_list
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|
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@ -27,26 +27,6 @@
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#define SIGNBIT (1u << 31)
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M68kCPU *cpu_m68k_init(struct uc_struct *uc, const char *cpu_model)
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{
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M68kCPU *cpu;
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CPUM68KState *env;
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ObjectClass *oc;
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oc = cpu_class_by_name(uc, TYPE_M68K_CPU, cpu_model);
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if (oc == NULL) {
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return NULL;
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}
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cpu = M68K_CPU(uc, object_new(uc, object_class_get_name(oc)));
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env = &cpu->env;
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register_m68k_insns(env);
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object_property_set_bool(uc, OBJECT(cpu), true, "realized", NULL);
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return cpu;
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}
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|
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void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
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{
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M68kCPU *cpu = m68k_env_get_cpu(env);
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|
|
|
@ -744,6 +744,10 @@ enum {
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#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
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#define cpu_init(uc, cpu_model) cpu_generic_init(uc, TYPE_MIPS_CPU, cpu_model)
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#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
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#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
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int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
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bool cpu_supports_isa(struct uc_struct *uc, const char *cpu_model, unsigned int isa);
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bool cpu_supports_cps_smp(struct uc_struct *uc, const char *cpu_type);
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|
|
|
@ -94,53 +94,6 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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return false;
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}
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static void sparc_cpu_parse_features(CPUState *cs, char *features,
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Error **errp);
|
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|
||||
static int cpu_sparc_register(struct uc_struct *uc, SPARCCPU *cpu, const char *cpu_model)
|
||||
{
|
||||
char *s = g_strdup(cpu_model);
|
||||
char *featurestr = strtok(s, ",");
|
||||
Error *err = NULL;
|
||||
|
||||
featurestr = strtok(NULL, ",");
|
||||
sparc_cpu_parse_features(CPU(cpu), featurestr, &err);
|
||||
g_free(s);
|
||||
if (err) {
|
||||
//error_report("%s", error_get_pretty(err));
|
||||
error_free(err);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SPARCCPU *cpu_sparc_init(struct uc_struct *uc, const char *cpu_model)
|
||||
{
|
||||
SPARCCPU *cpu;
|
||||
ObjectClass *oc;
|
||||
char *str, *name;
|
||||
|
||||
str = g_strdup(cpu_model);
|
||||
name = strtok(str, ",");
|
||||
oc = cpu_class_by_name(uc, TYPE_SPARC_CPU, name);
|
||||
g_free(str);
|
||||
if (oc == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cpu = SPARC_CPU(uc, object_new(uc, object_class_get_name(oc)));
|
||||
|
||||
if (cpu_sparc_register(uc, cpu, cpu_model) < 0) {
|
||||
object_unref(uc, OBJECT(cpu));
|
||||
return NULL;
|
||||
}
|
||||
|
||||
object_property_set_bool(uc, OBJECT(cpu), true, "realized", NULL);
|
||||
|
||||
return cpu;
|
||||
}
|
||||
|
||||
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
|
||||
{
|
||||
#if !defined(TARGET_SPARC64)
|
||||
|
@ -893,6 +846,7 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
|
|||
cc->reset = sparc_cpu_reset;
|
||||
|
||||
cc->class_by_name = sparc_cpu_class_by_name;
|
||||
cc->parse_features = sparc_cpu_parse_features;
|
||||
cc->has_work = sparc_cpu_has_work;
|
||||
cc->do_interrupt = sparc_cpu_do_interrupt;
|
||||
cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
|
||||
|
|
|
@ -568,7 +568,6 @@ void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
|
|||
|
||||
#ifndef NO_CPU_IO_DEFS
|
||||
/* cpu_init.c */
|
||||
SPARCCPU *cpu_sparc_init(struct uc_struct *uc, const char *cpu_model);
|
||||
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
|
||||
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
||||
/* mmu_helper.c */
|
||||
|
@ -643,16 +642,12 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
|
|||
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
|
||||
|
||||
#ifndef NO_CPU_IO_DEFS
|
||||
static inline CPUSPARCState *cpu_init(struct uc_struct *uc, const char *cpu_model)
|
||||
{
|
||||
SPARCCPU *cpu = cpu_sparc_init(uc, cpu_model);
|
||||
if (cpu == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
return &cpu->env;
|
||||
}
|
||||
#define cpu_init(uc, cpu_model) cpu_generic_init(uc, TYPE_SPARC_CPU, cpu_model)
|
||||
#endif
|
||||
|
||||
#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
|
||||
#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
|
||||
|
||||
#define cpu_signal_handler cpu_sparc_signal_handler
|
||||
#define cpu_list sparc_cpu_list
|
||||
|
||||
|
|
|
@ -256,7 +256,6 @@
|
|||
#define cptype_valid cptype_valid_x86_64
|
||||
#define cpu_abort cpu_abort_x86_64
|
||||
#define cpu_address_space_init cpu_address_space_init_x86_64
|
||||
#define cpu_arm_init cpu_arm_init_x86_64
|
||||
#define cpu_breakpoint_insert cpu_breakpoint_insert_x86_64
|
||||
#define cpu_breakpoint_remove cpu_breakpoint_remove_x86_64
|
||||
#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_x86_64
|
||||
|
|
Loading…
Reference in a new issue