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target/riscv: add vector extension field in CPURISCVState

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The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.

Backports ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 from qemu
This commit is contained in:
LIU Zhiwei 2021-02-26 02:12:56 -05:00 committed by Lioncash
parent fceb5e309a
commit 0968caa249
3 changed files with 14 additions and 0 deletions
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12
qemu/target/riscv/cpu.h
View file

@ -64,6 +64,7 @@
#define RVA RV('A')
#define RVF RV('F')
#define RVD RV('D')
#define RVV RV('V')
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
@ -93,9 +94,20 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
#define RV_VLEN_MAX 512
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
/* vector coprocessor state. */
uint64_t QEMU_ALIGNED(16, vreg[32 * RV_VLEN_MAX / 64]);
target_ulong vxrm;
target_ulong vxsat;
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
target_ulong pc;
target_ulong load_res;
target_ulong load_val;

1
qemu/target/riscv/translate.c
View file

@ -926,6 +926,7 @@ void riscv_translate_init(struct uc_struct *uc)
}
tcg_ctx->cpu_pc_risc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, pc), "pc");
tcg_ctx->cpu_vl_risc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, vl), "vl");
tcg_ctx->load_res_risc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, load_res),
"load_res");
tcg_ctx->load_val_risc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, load_val),

1
qemu/tcg/tcg.h
View file

@ -847,6 +847,7 @@ struct TCGContext {
TCGv_i64 cpu_fpr_risc[32]; /* assume F and D extensions */
TCGv load_res_risc;
TCGv load_val_risc;
TCGv cpu_vl_risc;
/* qemu/target-sparc/translate.c */
/* global register indexes */