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target-arm: lpae: Make t0sz and t1sz signed integers

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Make t0sz and t1sz signed integers to match tsz and to make
it easier to implement support for AArch32 negative t0sz.
t1sz is changed for consistensy.

No functional change.

Backports commit 5c31a10d16c595d6a59e3e7fc1808c3b1d03e02f from qemu
This commit is contained in:
Edgar E. Iglesias 2018-02-17 13:13:21 -05:00 committed by Lioncash
parent 7409da7a4e
commit 0c1c636b96
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target-arm/helper.c
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@ -5886,12 +5886,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
*/
uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
int32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
if (va_size == 64) {
t0sz = MIN(t0sz, 39);
t0sz = MAX(t0sz, 16);
}
uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
int32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
if (va_size == 64) {
t1sz = MIN(t1sz, 39);
t1sz = MAX(t1sz, 16);