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target/arm: Honour FPCR.FZ in FRECPX

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The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't actually care about the mantissa bits) but did
mean we were failing to set the FPSR.IDC bit.

Backports commit 2cfbf36ec07f7cac1aabb3b86f1c95c8a55424ba from qemu
This commit is contained in:
Peter Maydell 2018-06-02 10:02:37 -04:00 committed by Lioncash
parent a08dcb8aa6
commit 0f0b2e0bd8
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 0 deletions
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6
qemu/target/arm/helper-a64.c
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@ -382,6 +382,8 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
return nan;
}
a = float16_squash_input_denormal(a, fpst);
val16 = float16_val(a);
sbit = 0x8000 & val16;
exp = extract32(val16, 10, 5);
@ -411,6 +413,8 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
return nan;
}
a = float32_squash_input_denormal(a, fpst);
val32 = float32_val(a);
sbit = 0x80000000ULL & val32;
exp = extract32(val32, 23, 8);
@ -440,6 +444,8 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
return nan;
}
a = float64_squash_input_denormal(a, fpst);
val64 = float64_val(a);
sbit = 0x8000000000000000ULL & val64;
exp = extract64(float64_val(a), 52, 11);