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target/arm: Enable FEAT_SSBS for max AARCH64 CPU

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Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.

Backports 89455d1ba6ed190e840cb732e63958755ea42a07
This commit is contained in:
Rebecca Cran 2021-03-08 11:26:12 -05:00 committed by Lioncash
parent 01105515c7
commit 0f7620f7cc
1 changed files with 5 additions and 0 deletions
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5
qemu/target/arm/cpu64.c
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@ -301,6 +301,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
t = cpu->isar.id_aa64pfr1;
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
/*
* Begin with full support for MTE; will be downgraded to MTE=1
* during realize if the board provides no tag memory.
@ -349,6 +350,10 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
u = FIELD_DP32(u, ID_PFR0, DIT, 1);
cpu->isar.id_pfr0 = u;
u = cpu->isar.id_pfr2;
u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
cpu->isar.id_pfr2 = u;
u = cpu->isar.id_mmfr3;
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->isar.id_mmfr3 = u;