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target/arm: Enable FEAT_SSBS for max AARCH64 CPU
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1. Backports 89455d1ba6ed190e840cb732e63958755ea42a07
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@ -301,6 +301,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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t = cpu->isar.id_aa64pfr1;
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t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
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t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
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/*
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* Begin with full support for MTE; will be downgraded to MTE=1
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* during realize if the board provides no tag memory.
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@ -349,6 +350,10 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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u = FIELD_DP32(u, ID_PFR0, DIT, 1);
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cpu->isar.id_pfr0 = u;
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u = cpu->isar.id_pfr2;
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u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
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cpu->isar.id_pfr2 = u;
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u = cpu->isar.id_mmfr3;
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u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->isar.id_mmfr3 = u;
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