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target/arm: Flush high bits of sve register after AdvSIMD EXT

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Writes to AdvSIMD registers flush the bits above 128.

Backports commit 78cedfabd53b6f64e7e64fc84878d848e5df1d08 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:55:09 -04:00 committed by Lioncash
parent 96a96565db
commit 18e9c4805f
1 changed files with 1 additions and 0 deletions
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qemu/target/arm/translate-a64.c
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@ -7148,6 +7148,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_ctx, tcg_resl); tcg_temp_free_i64(tcg_ctx, tcg_resl);
write_vec_element(s, tcg_resh, rd, 1, MO_64); write_vec_element(s, tcg_resh, rd, 1, MO_64);
tcg_temp_free_i64(tcg_ctx, tcg_resh); tcg_temp_free_i64(tcg_ctx, tcg_resh);
clear_vec_high(s, true, rd);
} }
/* TBL/TBX /* TBL/TBX