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target/arm: Implement v8M MSPLIM and PSPLIM registers

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The v8M architecture includes hardware support for enforcing
stack pointer limits. We don't implement this behaviour yet,
but provide the MSPLIM and PSPLIM stack pointer limit registers
as reads-as-written, so that when we do implement the checks
in future this won't break guest migration.

Backports commit 57bb31568114023f67680d6fe478ceb13c51aa7d from qemu
This commit is contained in:
Peter Maydell 2018-03-08 09:42:01 -05:00 committed by Lioncash
parent 5812f7e3a3
commit 19baeb5120
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 48 additions and 0 deletions
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2
qemu/target/arm/cpu.h
View file

@ -502,6 +502,8 @@ typedef struct CPUARMState {
uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
uint32_t csselr[M_REG_NUM_BANKS];
uint32_t scr[M_REG_NUM_BANKS];
uint32_t msplim[M_REG_NUM_BANKS];
uint32_t psplim[M_REG_NUM_BANKS];
} v7m;
/* Information associated with an exception about to be taken:

46
qemu/target/arm/helper.c
View file

@ -9576,6 +9576,16 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
return 0;
}
return env->v7m.other_ss_psp;
case 0x8a: /* MSPLIM_NS */
if (!env->v7m.secure) {
return 0;
}
return env->v7m.msplim[M_REG_NS];
case 0x8b: /* PSPLIM_NS */
if (!env->v7m.secure) {
return 0;
}
return env->v7m.psplim[M_REG_NS];
case 0x90: /* PRIMASK_NS */
if (!env->v7m.secure) {
return 0;
@ -9617,6 +9627,16 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13];
case 9: /* PSP */
return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp;
case 10: /* MSPLIM */
if (!arm_feature(env, ARM_FEATURE_V8)) {
goto bad_reg;
}
return env->v7m.msplim[env->v7m.secure];
case 11: /* PSPLIM */
if (!arm_feature(env, ARM_FEATURE_V8)) {
goto bad_reg;
}
return env->v7m.psplim[env->v7m.secure];
case 16: /* PRIMASK */
return env->v7m.primask[env->v7m.secure];
case 17: /* BASEPRI */
@ -9625,6 +9645,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
case 19: /* FAULTMASK */
return env->v7m.faultmask[env->v7m.secure];
default:
bad_reg:
/* ??? For debugging only. */
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special"
" register %d\n", reg);
@ -9663,6 +9684,18 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
}
env->v7m.other_ss_psp = val;
return;
case 0x8a: /* MSPLIM_NS */
if (!env->v7m.secure) {
return;
}
env->v7m.msplim[M_REG_NS] = val & ~7;
return;
case 0x8b: /* PSPLIM_NS */
if (!env->v7m.secure) {
return;
}
env->v7m.psplim[M_REG_NS] = val & ~7;
return;
case 0x90: /* PRIMASK_NS */
if (!env->v7m.secure) {
return;
@ -9749,6 +9782,18 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.other_sp = val;
}
break;
case 10: /* MSPLIM */
if (!arm_feature(env, ARM_FEATURE_V8)) {
goto bad_reg;
}
env->v7m.msplim[env->v7m.secure] = val & ~7;
break;
case 11: /* PSPLIM */
if (!arm_feature(env, ARM_FEATURE_V8)) {
goto bad_reg;
}
env->v7m.psplim[env->v7m.secure] = val & ~7;
break;
case 16: /* PRIMASK */
env->v7m.primask[env->v7m.secure] = val & 1;
break;
@ -9781,6 +9826,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
break;
default:
bad_reg:
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special"
" register %d\n", reg);
return;