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riscv: Set xPIE to 1 after xRET

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When executing an xRET instruction, supposing xPP holds the
value y, xIE is set to xPIE; the privilege mode is changed to y;
xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.

Backports commit a37f21c27d3e2342c2080aafd4cfe7e949612428 from qemu
This commit is contained in:
Yiting Wang 2020-03-21 12:18:51 -04:00 committed by Lioncash
parent 6127f08028
commit 1c7f2083da
1 changed files with 2 additions and 2 deletions
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4
qemu/target/riscv/op_helper.c
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@ -92,7 +92,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
env->priv_ver >= PRIV_VERSION_1_10_0 ? env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_SIE : MSTATUS_UIE << prev_priv, MSTATUS_SIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_SPIE)); get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 0); mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv); riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus; env->mstatus = mstatus;
@ -117,7 +117,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
env->priv_ver >= PRIV_VERSION_1_10_0 ? env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv, MSTATUS_MIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_MPIE)); get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 0); mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv); riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus; env->mstatus = mstatus;