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target-arm: Use the right MMU index in arm_regime_using_lpae_format

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arm_regime_using_lpae_format checks whether the LPAE extension is used
for stage 1 translation regimes. MMU indexes not exclusively of a stage 1
regime won't work with this method.

In case of ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1, offset these values
by ARMMMUIdx_S1NSE0 to get the right index indicating a stage 1
translation regime.

Rename also the function to arm_s1_regime_using_lpae_format and update
the comments to reflect the change.

Backports commit deb2db996cbb9470b39ae1e383791ef34c4eb3c2 from qemu
This commit is contained in:
Alvise Rigo 2018-02-17 20:54:16 -05:00 committed by Lioncash
parent e4976f4597
commit 1e3e75fa44
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
17 changed files with 26 additions and 21 deletions
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2
qemu/aarch64.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_aarch64
#define arm_release arm_release_aarch64
#define arm_tlb_fill arm_tlb_fill_aarch64
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_aarch64
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_aarch64
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_aarch64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_aarch64
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_aarch64

2
qemu/aarch64eb.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_aarch64eb
#define arm_release arm_release_aarch64eb
#define arm_tlb_fill arm_tlb_fill_aarch64eb
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_aarch64eb
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_aarch64eb
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_aarch64eb
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_aarch64eb
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_aarch64eb

2
qemu/arm.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_arm
#define arm_release arm_release_arm
#define arm_tlb_fill arm_tlb_fill_arm
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_arm
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_arm
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_arm
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_arm
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_arm

2
qemu/armeb.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_armeb
#define arm_release arm_release_armeb
#define arm_tlb_fill arm_tlb_fill_armeb
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_armeb
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_armeb
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_armeb
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_armeb
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_armeb

2
qemu/header_gen.py
View file

@ -30,7 +30,7 @@ symbols = (
'address_space_stq_be',
'arm_release',
'arm_tlb_fill',
'arm_regime_using_lpae_format',
'arm_s1_regime_using_lpae_format',
'arm_cpu_do_unaligned_access',
'aarch64_sync_32_to_64',
'aarch64_sync_64_to_32',

2
qemu/m68k.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_m68k
#define arm_release arm_release_m68k
#define arm_tlb_fill arm_tlb_fill_m68k
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_m68k
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_m68k
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_m68k
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_m68k
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_m68k

2
qemu/mips.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_mips
#define arm_release arm_release_mips
#define arm_tlb_fill arm_tlb_fill_mips
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_mips
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_mips
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_mips
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_mips

2
qemu/mips64.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_mips64
#define arm_release arm_release_mips64
#define arm_tlb_fill arm_tlb_fill_mips64
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_mips64
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_mips64
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_mips64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips64
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_mips64

2
qemu/mips64el.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_mips64el
#define arm_release arm_release_mips64el
#define arm_tlb_fill arm_tlb_fill_mips64el
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_mips64el
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_mips64el
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_mips64el
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mips64el
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_mips64el

2
qemu/mipsel.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_mipsel
#define arm_release arm_release_mipsel
#define arm_tlb_fill arm_tlb_fill_mipsel
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_mipsel
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_mipsel
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_mipsel
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_mipsel
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_mipsel

2
qemu/powerpc.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_powerpc
#define arm_release arm_release_powerpc
#define arm_tlb_fill arm_tlb_fill_powerpc
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_powerpc
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_powerpc
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_powerpc
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_powerpc
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_powerpc

2
qemu/sparc.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_sparc
#define arm_release arm_release_sparc
#define arm_tlb_fill arm_tlb_fill_sparc
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_sparc
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_sparc
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_sparc
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_sparc
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_sparc

2
qemu/sparc64.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_sparc64
#define arm_release arm_release_sparc64
#define arm_tlb_fill arm_tlb_fill_sparc64
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_sparc64
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_sparc64
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_sparc64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_sparc64
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_sparc64

12
qemu/target-arm/helper.c
View file

@ -5339,11 +5339,15 @@ static inline bool regime_using_lpae_format(CPUARMState *env,
return false;
}
/* Returns true if the translation regime is using LPAE format page tables.
* Used when raising alignment exceptions, whose FSR changes depending on
* whether the long or short descriptor format is in use. */
bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
/* Returns true if the stage 1 translation regime is using LPAE format page
* tables. Used when raising alignment exceptions, whose FSR changes depending
* on whether the long or short descriptor format is in use. */
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
{
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
mmu_idx += ARMMMUIdx_S1NSE0;
}
return regime_using_lpae_format(env, mmu_idx);
}

5
qemu/target-arm/internals.h
View file

@ -443,8 +443,9 @@ struct ARMMMUFaultInfo {
bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
uint32_t *fsr, ARMMMUFaultInfo *fi);
/* Return true if the translation regime is using LPAE format page tables */
bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
/* Return true if the stage 1 translation regime is using LPAE format page
* tables */
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
/* Raise a data fault alignment exception for the specified virtual address */
void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,

2
qemu/target-arm/op_helper.c
View file

@ -149,7 +149,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
/* the DFSR for an alignment fault depends on whether we're using
* the LPAE long descriptor format, or the short descriptor format
*/
if (arm_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
env->exception.fsr = 0x21;
} else {
env->exception.fsr = 0x1;

2
qemu/x86_64.h
View file

@ -24,7 +24,7 @@
#define address_space_stq_be address_space_stq_be_x86_64
#define arm_release arm_release_x86_64
#define arm_tlb_fill arm_tlb_fill_x86_64
#define arm_regime_using_lpae_format arm_regime_using_lpae_format_x86_64
#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_x86_64
#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_x86_64
#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_x86_64
#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_x86_64