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target-sparc: implement UltraSPARC-T1 Strand status ASR

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Backports commit b8e31b3cc6315bc5c6ec686c363c088c4fb1d0ea from qemu
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Artyom Tarasenko 2018-03-01 20:43:45 -05:00 committed by Lioncash
parent 2f329af7ef
commit 204a4dc1d3
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1 changed files with 11 additions and 0 deletions
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qemu/target-sparc/translate.c
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@ -3631,6 +3631,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
case 0x19: /* System tick compare */ case 0x19: /* System tick compare */
gen_store_gpr(dc, rd, tcg_ctx->cpu_stick_cmpr); gen_store_gpr(dc, rd, tcg_ctx->cpu_stick_cmpr);
break; break;
case 0x1a: /* UltraSPARC-T1 Strand status */
/* XXX HYPV check maybe not enough, UA2005 & UA2007 describe
* this ASR as impl. dep
*/
CHECK_IU_FEATURE(dc, HYPV);
{
TCGv t = gen_dest_gpr(dc, rd);
tcg_gen_movi_tl(tcg_ctx, t, 1UL);
gen_store_gpr(dc, rd, t);
}
break;
case 0x10: /* Performance Control */ case 0x10: /* Performance Control */
case 0x11: /* Performance Instrumentation Counter */ case 0x11: /* Performance Instrumentation Counter */
case 0x12: /* Dispatch Control */ case 0x12: /* Dispatch Control */