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util/cacheinfo: Fix warning generated by clang

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Clang generates the following warning on aarch64 host:

CC util/cacheinfo.o
/home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^
/home/pranith/qemu/util/cacheinfo.c:121:28: note: use constraint modifier "w"
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^~
%w0

Constraint modifier 'w' is not (yet?) accepted by gcc. Fix this by increasing the ctr size.

Backports commit 2ae96c157ab3155baf6595c08cf5d3fe3c023a60 from qemu
This commit is contained in:
Pranith Kumar 2018-03-03 22:04:08 -05:00 committed by Lioncash
parent 57f8eec080
commit 2141c777f1
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 1 deletions
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qemu/util/cacheinfo.c
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@ -110,7 +110,7 @@ static void sys_cache_info(int *isize, int *dsize)
static void arch_cache_info(int *isize, int *dsize)
{
if (*isize == 0 || *dsize == 0) {
unsigned ctr;
unsigned long ctr;
/* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
but (at least under Linux) these are marked protected by the