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target/riscv: Enable vector extensions

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This commit is contained in:
Lioncash 2021-03-07 13:03:51 -05:00
parent dba0d32708
commit 23dc2fb4a2
2 changed files with 9 additions and 1 deletions
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5
qemu/target/riscv/cpu.c
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@ -308,6 +308,11 @@ static void riscv_cpu_reset(CPUState *cs)
cs->exception_index = EXCP_NONE; cs->exception_index = EXCP_NONE;
env->load_res = -1; env->load_res = -1;
set_default_nan_mode(1, &env->fp_status); set_default_nan_mode(1, &env->fp_status);
// Unicorn: Allow vector operations.
cpu->cfg.ext_v = true;
cpu->cfg.elen = 64;
cpu->cfg.vlen = 128;
} }
// Unicorn: if'd out // Unicorn: if'd out

5
qemu/target/riscv/cpu.h
View file

@ -97,7 +97,7 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h" #include "pmp.h"
#define RV_VLEN_MAX 512 #define RV_VLEN_MAX 256
FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VSEW, 2, 3)
@ -287,8 +287,11 @@ typedef struct RISCVCPU {
CPURISCVState env; CPURISCVState env;
struct { struct {
bool ext_v;
bool ext_ifencei; bool ext_ifencei;
bool ext_icsr; bool ext_icsr;
char *vext_spec;
uint16_t vlen; uint16_t vlen;
uint16_t elen; uint16_t elen;
} cfg; } cfg;