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target-mips: correct MTC0 instruction on MIPS64

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MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.

Backports commit d54a299b83a07642c85a22bfe19b69ca4def9ec4 from qemu
This commit is contained in:
Leon Alrae 2018-02-15 16:30:43 -05:00 committed by Lioncash
parent 18dcbc7a64
commit 2a968bb547
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 12 deletions
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19
qemu/target-mips/translate.c
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@ -4831,13 +4831,6 @@ static inline void gen_mtc0_store32 (DisasContext *ctx, TCGv arg, target_ulong o
tcg_temp_free_i32(tcg_ctx, t0); tcg_temp_free_i32(tcg_ctx, t0);
} }
static inline void gen_mtc0_store64 (DisasContext *ctx, TCGv arg, target_ulong off)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, off);
}
static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
{ {
TCGContext *s = ctx->uc->tcg_ctx; TCGContext *s = ctx->uc->tcg_ctx;
@ -5701,12 +5694,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 5: case 5:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_VPESchedule)); tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule"; rn = "VPESchedule";
break; break;
case 6: case 6:
CP0_CHECK(ctx->insn_flags & ASE_MT); CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack"; rn = "VPEScheFBack";
break; break;
case 7: case 7:
@ -5955,7 +5950,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 14: case 14:
switch (sel) { switch (sel) {
case 0: case 0:
gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_EPC)); tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC"; rn = "EPC";
break; break;
default: default:
@ -6128,7 +6123,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (sel) { switch (sel) {
case 0: case 0:
/* EJTAG support */ /* EJTAG support */
gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_DEPC)); tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC"; rn = "DEPC";
break; break;
default: default:
@ -6231,7 +6226,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 30: case 30:
switch (sel) { switch (sel) {
case 0: case 0:
gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_ErrorEPC)); tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC"; rn = "ErrorEPC";
break; break;
default: default: