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target-arm: Add condexec state to insn_start

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Backports commit 52e971d9ff67e340ac2a86bd67e14bd31c7991e0 from qemu
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Richard Henderson 2018-02-11 15:13:29 -05:00 committed by Lioncash
parent 3f9502dc8b
commit 2c091e5fb8
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 4 additions and 2 deletions
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1
qemu/target-arm/cpu.h
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@ -102,6 +102,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
struct arm_boot_info;
#define NB_MMU_MODES 4
#define TARGET_INSN_START_EXTRA_WORDS 1
/* We currently assume float and double are IEEE single and double
precision respectively.

2
qemu/target-arm/translate-a64.c
View file

@ -11279,7 +11279,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
tcg_ctx->gen_opc_instr_start[lj] = 1;
//tcg_ctx->gen_opc_icount[lj] = num_insns;
}
tcg_gen_insn_start(tcg_ctx, dc->pc);
tcg_gen_insn_start(tcg_ctx, dc->pc, 0);
num_insns++;
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {

3
qemu/target-arm/translate.c
View file

@ -11477,7 +11477,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
tcg_ctx->gen_opc_instr_start[lj] = 1;
//tcg_ctx->gen_opc_icount[lj] = num_insns;
}
tcg_gen_insn_start(tcg_ctx, dc->pc);
tcg_gen_insn_start(tcg_ctx, dc->pc,
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1));
num_insns++;
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {